Abstract
SiC MOSFETs integrated with Junction-Barrier-Schottky diode (JMOS) are used in many applications due to no bipolar degradation problem, but there is still not much research on SPICE modeling of JMOS. In this paper, a high-accuracy SPICE model based on measured data is established. The model mainly includes five parts: core MOSFET, gate resistance, junction capacitance, stray inductance, and embedded diode. To reduce the relative error of static characteristics, the drain-source current setting of the core MOSFET is optimized, and the characteristics of electron mobility as a function of gate voltage are characterized. Based on the C-V characteristics of JMOS, the junction capacitance value is characterized as a nonlinear function of voltage. The relative error between the simulation results and the measured data is less than 6.5%. This confirms the accuracy and generality of the model, which is suitable for system-level circuit simulation based on JMOS. The proposed model has a reference value for the modeling of most vertical MOSFETs integrated with the Junction-Barrier-Schottky diode.
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Acknowledgments
This work was funded by the National Key Research and Development Program of China under Grant 2021YFB2500601, “Pioneer” R&D Program of Zhejiang under Grant 2022C01235, Open Fund Project 2021KF001 of the State Key Laboratory of Wide Bandgap Semiconductor Power Electronic Devices.
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Shao, F. et al. (2023). SPICE Modeling of Three Novel SiC MOSFETs with Integrated Junction-Barrier-Schottky Diode. In: Yang, Q., Li, J., Xie, K., Hu, J. (eds) The Proceedings of the 17th Annual Conference of China Electrotechnical Society. ACCES 2022. Lecture Notes in Electrical Engineering, vol 1012. Springer, Singapore. https://doi.org/10.1007/978-981-99-0357-3_130
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DOI: https://doi.org/10.1007/978-981-99-0357-3_130
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