Abstract
A modular reduction unit is a primary element of Residue Number Systems and cryptography implementations. The modular reduction unit is required to perform cryptographic algorithms such as Elliptical Curve Cryptography (ECC) and Digital Signature Algorithms (DSA). The operation of modular reduction unit is utilized in various modular arithmetic such as modular addition, modular multiplication, and division. In this paper, three binary adders are developed using Switching Activity (SA). The proposed binary adder is designed using the logic decomposition method. Based on the presented full adders, the Modular Reduction Unit (MRU) is enhanced. Three MRUs are simulated and synthesized using Xilinx Viva-do Zynq-7000 device. From the synthesis results, the proposed modular reduction unit is improved in terms of total cell count and dynamic power consumption by (56% and 46%) over the conventional and modified conventional methods. Power Delay Product and Energy delay Product of the proposed MRU is enhanced by (~56%, ~ 44%) over the conventional and modified conventional methods.
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Pakkiraiah, C., Satyanarayana, R.V.S. (2023). Design of Low Power Modular (x mod p) Reduction Unit Based on Switching Activity for Data Security Applications. In: Darji, A.D., Joshi, D., Joshi, A., Sheriff, R. (eds) Advances in VLSI and Embedded Systems. Lecture Notes in Electrical Engineering, vol 962. Springer, Singapore. https://doi.org/10.1007/978-981-19-6780-1_2
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DOI: https://doi.org/10.1007/978-981-19-6780-1_2
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