A Unified Libraries for GDI Logic to Achieve Low-Power and High-Speed Circuit Design

Abstract

Several monumental vicissitudes have occurred in IC design industry in various fields of electronics. The challenge of circuit design is addressed by numerous multifaceted optimization approaches such as the technology castoff for the implementation of design, the topologies in realization, the circuits, architectures and algorithm. Therefore, in product development, the trade-off exists between area-power-speed and optimal ASIC library. This work reveals a paradigm of GDI library creation which supports for designing combinational and sequential logic circuit for low-power and high-speed applications. This work demonstrates four different GDI library pattern creations with and without level restoration circuits. The experimentation was done using Silterra 130 nm process mentor graphics Pyxis software and the parameter like rise time, fall time, delay power and dynamic power have been analysed. These four library cells are compared with the existing counterpart CMOS technology and reveal the significant improvement in terms of transistor count, delay and power.