Abstract
Low power is applied while designing a chip and it is the important challenge faced by VLSI designer. Interconnections and internal parameters of bulk connections will consume maximum amount of power when the technology shrinks, when data is transmitted to bus architecture it consumes a significant amount of power, and when transitions occur more power is required, and hence power has to be saved. Switching activity power can be minimized by design and controlling encoding system in the network and power is altered with voltage from the supply rails and interconnected capacitance. Minimization of the capacitance by using charging and discharging activity which is nothing but a encoding techniques. A new technique is proposed in nanometer technology.
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Vennapusapalli, S., Sreerama Reddy, G.M., Patel, R.R. (2021). Analysis of Coupling Transition for the Encoded Data and Its Logical Level Power Analysis. In: Reddy, K.A., Devi, B.R., George, B., Raju, K.S. (eds) Data Engineering and Communication Technology. Lecture Notes on Data Engineering and Communications Technologies, vol 63. Springer, Singapore. https://doi.org/10.1007/978-981-16-0081-4_19
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DOI: https://doi.org/10.1007/978-981-16-0081-4_19
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