Abstract
In this paper, a distributed clock gating technique is applied to a 32-bit ALU. The ALU design performs all the fundamental arithmetic and logical operations based on the selection of the operations. The system operates at 250 MHz clock frequency. Clock gating is the predominant technique applied to circuits to avoid unnecessary switching activity, leading to power consumptions. Here, the ALU designed is segregated as two functional modules, and the clock gating is applied, leading to distributed clock gating. The design is analyzed for gray code and random test patterns, and it is observed that gray code data representation consumes less power. The 32-bit ALU is implemented for a 45 nm technology using CADENCE tool. Simulation results show that the hierarchical and distributed clock gating techniques aid in power reduction to nearly 45% to 50%, depending on the transitions on the input signals with an increase in area by 2% to 3%. The gray code input test patterns provide better power reduction as compared to traditional random inputs.
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Kulkarni, R.R., Kulkarni, S.Y. (2020). Power Optimization of a 32-Bit ALU Using Distributed Clock Gating Technique. In: Sengodan, T., Murugappan, M., Misra, S. (eds) Advances in Electrical and Computer Technologies. Lecture Notes in Electrical Engineering, vol 672. Springer, Singapore. https://doi.org/10.1007/978-981-15-5558-9_71
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DOI: https://doi.org/10.1007/978-981-15-5558-9_71
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