Abstract
The arithmetic operation is the most crucial part in VLSI technology. Multiplication plays a significant role in arithmetic operations of various VLSI systems. The digital multipliers are used in realizing many DSP computations like FFT, MAC, and DFT. By calculating the silicon area, power, speed, and delay, the performance of the circuit is evaluated. In this paper, we used the ancient Vedic mathematics for implementation of the factorial circuit in the physical design level. The ancient Vedic mathematics (AVM)-based calculations are faster than the conventional-based calculations. An innovative idea to design an AVM-based factorial circuit is suggested in this work. In this paper, the proposed multiplier is designed by using AVM-based algorithm called Urdhva-Tiryagbhyam (UT), which is used to calculate the factorial of binary numbers. The proposed factorial circuit is designed by using the UT-based Vedic multiplier, incrementer, decrementer, zero detector, and a comparator with the help of Verilog HDL. It is synthesized and simulated using the Cadnce EDA (NC Sim,RTL Compiler, Encounter) tool in digital level. The result obtained in this work is found to be correct as well as meticulous.
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Acknowledgements
All the simulations, synthesis, and implementation are done in Laboratory of Centurion University of Technology & Management, Odisha, India. Authors gratefully acknowledge to the University for providing research scope.
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Panda, S.K., Sahoo, A., Panda, D.C. (2020). Design and Implementation of a Factorial Circuit for Binary Numbers: An AVM-Based VLSI Computing Approach. In: Pati, B., Panigrahi, C., Buyya, R., Li, KC. (eds) Advanced Computing and Intelligent Engineering. Advances in Intelligent Systems and Computing, vol 1089. Springer, Singapore. https://doi.org/10.1007/978-981-15-1483-8_7
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DOI: https://doi.org/10.1007/978-981-15-1483-8_7
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