Abstract
In this paper, we present the implementation of artificial neural networks in the FPGA embedded platform. The implementation is done by two different methods: a hardware implementation and a softcore implementation, in order to compare their performances and to choose the one that best approaches real-time systems and processes. For this, we have exploited the tools of this platform such as blocks Megafunctions and softcore NIOS II processor. The results obtained in terms of execution time have shown that the hardware implementation is much more efficient than that based on the NIOS II softcore.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Mellit, A., Mekki, H., Messai, A., Kalogirou, S.A.: FPGA-based implementation of intelligent predictor for global solar irradiation, part I: theory and simulation. Expert. Syst Appl. 38(3), 2668–2685 (2011)
Savich, A.W., Moussa, M., Areibi, S.: The impact of arithmetic representation on implementing MLP-BP on FPGAs: a study. IEEE Trans. Neural Netw. 18(1), 240–252 (2007)
Shah, N., Chaudhari, P., Varghese, K.: Runtime programmable and memory bandwidth optimized FPGA-based coprocessor for deep convolutional neural network. IEEE Trans. Neural Netw. Learn. Syst. 99, 1–13 (2018)
Sun, Y., Cheng, A.C.: Machine learning on-a-chip: a high-performance low-power reusable neuron architecture for artificial neural networks in ECG classifications. Comput. Biol. Med. 42, 751757 (2012)
Roy Chowdhury, S., Saha, H.: Development of a FPGA based fuzzy neural network system for early diagnosis of critical health condition of a patient. Comput. Biol. Med. 40(2), 190–200 (2010)
Mohamed, A., Issam, A., Mohamed, B., Abdellatif, B.: Real-time detection of vehicles using the haar-like features and artificial neuron networks. Procedia Comput. Sci. 73, 24–31 (2015)
Atibi, M., Atouf, I., Boussaa, M., Bennis, A.: Comparison between the MFCC and DWT applied to the roadway classification. In: 2016 7th International Conference on Computer Science and Information Technology (CSIT), pp. 1–6. IEEE (2016)
Mohamed, B., Issam, A., Mohamed, A., Abdellatif, B.: ECG image classification in real time based on the haar-like features and artificial neural networks. Procedia Comput. Sci. 73, 32–39 (2015)
Boussaa, M., Atouf, I., Atibi, M., Bennis, A.: Comparison of MFCC and DWT features extractors applied to PCG classification. In: 2016 11th International Conference on Intelligent Systems: Theories and Applications (SITA), pp. 1–5. IEEE (2016)
Boussaa, M., Atouf, I., Atibi, M., Bennis, A.: ECG signals classification using MFCC coefficients and ANN classifier. In: 2016 International Conference on Electrical and Information Technologies (ICEIT), pp. 480–484. IEEE (2016)
Yadan, O., Adams, K., Taigman, Y., Ranzato, M.A.: Multi-gpu training of convnets. arXiv preprint arXiv:1312.5853 (2013)
Chen, Y.H., Krishna, T., Emer, J.S., Sze, V.: Eyeriss: an energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J. Solid-State Circuits 52(1), 127–138 (2017)
Zhang, D., Wang, Q., Xu, C.: Data acquisition system of a self-balancing robot based on FPGA. J. Theor. Appl. Inf. Technol. 47(2) (2013)
Lin, C.J., Tsai, H.M.: FPGA implementation of a wavelet neural network with particle swarm optimization learning. Math. Comput. Model. 47(9), 982–996 (2008)
Atibi, M., Bennis, A., Boussaa, M.: Precise calculation unit based on a hardware implementation of a formal neuron in a FPGA platform. Int. J. Adv. Eng. Technol. 7(3) (2014)
Boussaa, M., Bennis, A., Atibi M.: Comparison between two hardware implementations of a formal neuron on FPGA platform. Int. J. Innov. Technol. Explor. Eng. 4(1) (2014)
Alin, M., Pehlivan, I., Koyuncu, I.: Hardware design and implementation of a novel ANN-based chaotic generator in FPGA. Optik (Stuttg) 127(13), 5500–5505 (2016)
Mohammed, H.K., Ali, E.Z.: Hardware implementation of artificial neural network using field programmable gate array. Int. J. Comput. Theory Eng. 5(5), 780 (2013)
Atibi, M., Atouf, I., Boussaa, M., Bennis, A.: Parallel and mixed hardware implementation of artificial neuron network on the FPGA platform. Int. J. Eng. Technol. 6(5), 0975–4024 (2014)
Pokale, M.S.M., Kulkarni, M.K., Rode, S.V.: NIOS II processor implementation in FPGA: an application of data logging system. Int. J. Sci. Technol. Res. 1(11) (2012)
Mukadam, M.S.B., Titarmare, A.S.: Design of power optimization using C2H hardware accelerator and NIOS II processor (2014)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2020 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Atibi, M., Boussaa, M., Bennis, A., Atouf, I. (2020). Real-Time Implementation of Artificial Neural Network in FPGA Platform. In: Bhateja, V., Satapathy, S., Satori, H. (eds) Embedded Systems and Artificial Intelligence. Advances in Intelligent Systems and Computing, vol 1076. Springer, Singapore. https://doi.org/10.1007/978-981-15-0947-6_1
Download citation
DOI: https://doi.org/10.1007/978-981-15-0947-6_1
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-15-0946-9
Online ISBN: 978-981-15-0947-6
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)