Impact of Spacer Engineering on Hybrid Channel Junctionless Transistor Performance

Abstract

This work reports the effect of spacer engineering on the device performance of hybrid channel junctionless transistor. Hybrid channel junctionless transistor suppresses the parasitic BJT action in junctionless transistor by using body profile engineering. It consists of the highly doped $P^{+}$ substrate beneath the $N^{+}$ active channel and high-K spacers on both side of the gate, termed as hybrid channel junctionless transistor with spacer (HC-JLT). This $P^{+}$ layer reduces the effective channel thickness and results in better gate controllability in channel region, and it also expedites the depletion region near the drain and the channel interface, which in turn increases the tunneling barrier width for the OFF-state and decreases the tunneling of electrons. This incorporated $P^{+}$ layer also acts as hole sink and provides a path to holes generated due to the band-to-band tunneling (BTBT). Using calibrated 2-D TCAD simulation study, we have analyzed the impact of high-K sidewall spacer on HC-JLT performance. This sidewall high-K spacer tailors electric field below the flat band condition, and it increases the effective channel length ($L_{ {eff}}$) by depleting channel region in the OFF-state. The analysis shows the immense potential of HC-JLT as potential enabler for futuristic low-power, high-speed and ultra-scaled transistor.