Abstract
One of the simpler techniques, which involve the implementation of generating the address of two-dimensional deinterleaver used in the WiMAX transmitter and receiver block is proposed using the Xilinx FPGA. The Arithmetic and Logic Unit performs various mathematical operations such as addition, subtraction, division and many other logical operations. Apart from these operations, Multiplication is one of the most fundamental operations to be carried out by this unit. The implementation of multipliers is required for the address generation of the channel interleaver. The multipliers need to be designed in such a way that they require high speed, low power, less area, and less delay, which is of significant interest in the research area. Many attempts have been carried out to reduce the generation of number of partial products in the process of multiplication. Array multiplier is one such multiplier. Most of the arithmetic operations will be performed using multipliers which consume the majority amount of the power in digital circuits. The process of multiplication involves the shift and add operations. The performance of multiplier can be improved by optimizing the adder circuit. The objective of this paper is to build the algorithm for generating the address of channel deinterleaver by using modified array multiplier. The algorithm is built using the Hardware Description Language Verilog and the functioning of the system can be verified through simulation and implemented using the Spartan-6. The simulation and implementation results have been obtained for the three different modulation techniques such as QPSK, 16-QAM, and 64-QAM for some of the information rates which proves to be a very good technique against the conventional methods.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Konhauser, W. (2006). Broadband wireless access solutions-Progressive challenges and potential value of next generation. Wireless Personal Communications, 37(3/4), 243–259.
Li, B., Qin, Y., Low, C. P., & Gwee, C. L. (2007). A survey on mobile WiMAX. IEEE Communications Magazine, 45(12), 70–75.
Andrews, J. G., Ghosh, A., & Muhamed, R. (2007). Fundamentals of WiMAX: Understanding broadband wireless networking. Upper Saddle River, NJ, USA: Prentice-Hall.
Chang, Y. N., & Ding, Y. C. (2007). A low-cost dual mode de-interleaver design. In Proceedings of International Conference on Consumer Electronics (pp. 1–2).
Khater, A. A., Khairy, M. M.,& Habib, S. E. D. (2009). Efficient FPGA implementation for the IEEE 802.16e interleaver. In Proceedings of International Conference on Microelectronics (pp. 181–184). Marrakech, Morocco.
Upadhyaya, B. K., Misra, I. S., & Sanyal, S. K. (2010). Novel design of address generator for WiMAX multimode interleaver using FPGA based finite state machine. In Proceedings of 13th International Conference on Computer and Information Technology (pp. 153–158). Dhaka, Bangladesh.
Asghar, R., & Liu, D. (2009). 2D realization of WiMAX channel interleaver for efficient hardware implementation. In Proceedings of World Academy of Science, Engineering and Technology (vol. 51, pp. 25–29), Hong Kong.
IEEE Standard for Local and Metropolitan Are Networks-Part 16: Air Interface for Fixed Broadband Wireless Access Systems-Amendment 2. (2005). IEEE Std. 802.16e-2005.
Khan, M. N., & Ghauri, S. (2008). The WiMAX 802.16e physical layer model. In Proceedings of IET Conference on Wireless, Mobile and Multimedia Networks (pp. 117–120). Mumbai, India.
Wallace, C. A suggestion for a fast multiplier. IEEE Transaction on Electronic Computers.
Nikita, P., & Kakhandki, A. (2017). Study of low power array multiplier for real time applications. International Journal of Research and Advanced Development (IJRAD), 1(3).
Srikanth, S., et al. (2016). Low power array multiplier using modified full adder. In 2016 IEEE International Conference on Engineering and Technology (ICETECH). IEEE.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2019 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Nikita, P., Kakhandki, A., Ramakrishna, S., Kumar, P. (2019). Implementation of Modified Array Multiplier for WiMAX Deinterleaver Address Generation. In: Shetty, N., Patnaik, L., Nagaraj, H., Hamsavath, P., Nalini, N. (eds) Emerging Research in Computing, Information, Communication and Applications. Advances in Intelligent Systems and Computing, vol 882. Springer, Singapore. https://doi.org/10.1007/978-981-13-5953-8_52
Download citation
DOI: https://doi.org/10.1007/978-981-13-5953-8_52
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-13-5952-1
Online ISBN: 978-981-13-5953-8
eBook Packages: EngineeringEngineering (R0)