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FOWLP: Chip-First and Die Face-Down

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Fan-Out Wafer-Level Packaging

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Abstract

The first fan-out wafer-level packaging (FOWLP) U.S. patent was filed by Infineon on October 31, 2001 (Hedler et al. in Transfer Wafer Level Packaging, 2001 [1]; Lau in Chip Scale Rev. 19:42–46, 2015 [2]), and the first technical papers were also published (at ECTC2006 and EPTC2006) by Infineon and their industry partners: Nagase, Nitto Denko, and Yamada (Brunnbauer et al. in IEEE/ECTC Proceedings, 547–551, 2006 [3]; Brunnbauer et al. in IEEE/EPTC Proceedings, 1–5, 2006 [4]). At that time, they called it embedded wafer-level ball (eWLB) grid array.

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Authors and Affiliations

  1. ASM Pacific Technology, Hong Kong, New Territories, Hong Kong

    John H. Lau

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  1. John H. Lau
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Correspondence to John H. Lau .

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Lau, J.H. (2018). FOWLP: Chip-First and Die Face-Down. In: Fan-Out Wafer-Level Packaging. Springer, Singapore. https://doi.org/10.1007/978-981-10-8884-1_5

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  • DOI: https://doi.org/10.1007/978-981-10-8884-1_5

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  • Print ISBN: 978-981-10-8883-4

  • Online ISBN: 978-981-10-8884-1

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