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Fan-in Wafer-Level Packaging Versus FOWLP

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Fan-Out Wafer-Level Packaging
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Abstract

Fan-in wafer-level packaging (WLP) technology will be discussed in this chapter. A wafer-level chip scale package (WLCSP) will be designed and fabricated, and then assembled on a printed circuit board (PCB). Emphasis is placed on the key process steps in making the redistribution layer (RDL) of the WLCSP and its PCB solder joint reliability.

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References

  1. Lau, J.H., and S.W.R. Lee. 1999. Chip Scale Package. New York: McGraw-Hill Book Company.

    Google Scholar 

  2. Lau, J.H., T. Chung, R. Lee, C. Chang, and C. Chen. 1999. A Novel and Reliable Wafer-Level Chip Scale Package (WLCSP). In Proceedings of the Chip Scale International Conference, SEMI, September 1999, H1–8.

    Google Scholar 

  3. Elenius, P. 1998. Flip Chip Bumping for IC Packaging Contractors. In Proceedings of NEPCON West, Anaheim, CA, February 1998, 1403–1407.

    Google Scholar 

  4. Wu, M., S. Chung, and D. Yu. 2016. UFI (UBM-free integration) Fan-in WLCSP Technology Enables Large Die Fine-Pitch Packages. In IEEE/ECTC Proceedings, May 2016, 1154–1159.

    Google Scholar 

  5. Yasunaga, M., S. Baba, M. Matsuo, H. Matsushima, S. Nakao, and T. Tachikawa. 1994. Chip Scale Package: A Lightly Dressed LSI Chip. In Proceedings of IEEE/CPMT International Electronics Manufacturing Technology Symposium, La Jolla, CA, 1994, 169–176.

    Google Scholar 

  6. Marcoux, P. 1994. A Minimal Packaging Solution for Known Good Die And Direct Chip Attachment. In Proceedings of Surface Mount International Conference, San Jose, CA, August 1994, 19–26.

    Google Scholar 

  7. Chanchani, R., K. Treece, and P. Dressendorfer. 1995. A New Mini Ball Grid Array (m-BGA) Multichip Module Technology. In Proceedings of NEPCON West, February 1995, 938–945.

    Google Scholar 

  8. Badihi, A., and E. Por. 1995. Shellcase—A True Miniature Integrated Circuit Package. In Proceedings of International FC, BGA, Advanced Packaging Symposium, San Jose, CA, February 1995, pp. 244–252.

    Google Scholar 

  9. Baba, S., Y. Tomita, M. Matsuo, H. Matsushima, N. Ueda, and O. Nakagawa. 1996. Molded Chip Scale Package for High Pin Count. In Proceedings of IEEE/ECTC, Orlando, FL, May 1996, 1251–1257.

    Google Scholar 

  10. Topper, M., J. Simon, and H. Reichl. 1996. Redistribution Technology For Chip Scale Package Using Photosensitive BCB. Future Fab International, 363–368.

    Google Scholar 

  11. Auersperg, J., D. Vogel, J. Simon, A. Schubert, and B. Michel. 1997. Reliability Evaluation of Chip Scale Packages by FEA and microDAC. In Proceedings of Symposium on Design and Reliability of Solder and Solder Interconnections, TMS Annual Meeting, Orlando, FL, 1997, 439–445.

    Google Scholar 

  12. DiStefano, T. 1997. Wafer-Level Fabrication of IC Packages. Chip Scale Review, 20–27.

    Google Scholar 

  13. Kohl, J.E., C.W. Eichellerger, S.K. Phillips, and M.E. Rickley. 1997. Low Cost Chip Scale Packaging and Interconnect Technology. In Proceedings of the CSP Symposium, San Jose, CA, 1997, 37–43.

    Google Scholar 

  14. Lau, J.H., C. Chang, and S.W.R. Lee. 2000. Solder Joint Creak Propagation Analysis of Wafer-Level Chip Scale Packages on Printed Circuit Board Assemblies. In IEEE/ECTC Proceedings, 1360–1368.

    Google Scholar 

  15. Lau, J.H., S.W.R. Lee, and C. Chang. 2000. Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis. ASME Transactions Journal of Electronic Packaging 122 (4): 311–316.

    Article  Google Scholar 

  16. Lau, J.H., S.W.R. Lee, and C. Chang. 2001. Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies. IEEE Transactions on CPMT, 285–292.

    Google Scholar 

  17. Lau, J.H., S. Pan, and C. Chang. 2001. Nonlinear Fracture Mechanics Analysis of Wafer Level Chip Scale Package Solder Joints with Cracks. The International Journal of Microcircuits and Electronic Packaging 24 (1): 1–10 (First Quarter).

    Google Scholar 

  18. Lau, J.H., S. Pan, and C. Chang. 2002. A New Thermal-Fatigue Life Prediction Model for Wafer Level Chip Scale Package (WLCSP) Solder Joints. ASME Transactions Journal of Electronic Packaging 124 (3): 212–220.

    Article  Google Scholar 

  19. Lau, J.H., S. Pan, and C. Chang. 2000. Nonlinear Fracture Mechanics Analysis of Wafer-Level Chip Scale Package Solder Joints with Cracks. In Proceedings of IMAPS Microelectronics Conference, 857–865.

    Google Scholar 

  20. Lau, J.H., and Y. Pao. 1997. Solder Joint Reliability. New York: McGraw-Hill Book Company.

    Google Scholar 

  21. Lau, J.H. 2011. Reliability of RoHS-Compliant 2D and 3D Interconnects. New York: McGraw-Hill Book Company.

    Google Scholar 

  22. Shangguan, D. 2005. Lead-Free Solder Interconnect Reliability. Materials Park, OH: ASM International.

    Google Scholar 

  23. Tobias, P., and D. Trindade. 1995. Applied Reliability. New York: Van Nostrand Reinhold.

    MATH  Google Scholar 

  24. Lipson, C., and N. Sheth. 1973. Statistical Design and Analysis of Engineering Experiments. New York: McGraw-Hill Book Company.

    Google Scholar 

  25. Ang, A., and W. Tang. 1981. Probability Concept in Engineering Planning and Design. New York: Wiley.

    Google Scholar 

  26. Grant, E., and R. Leavenworth. 1980. Statistical Quality Control. New York: McGraw-Hill Book Company.

    MATH  Google Scholar 

  27. Lee, C.K., T.C. Chang, J.H. Lau, Y. Huang, H. Fu, J. Huang, Z. Hsiao, C. Ko, R. Cheng, P. Chang, K. Kao, Y. Lu, R. Lo, and M. Kao. 2012. Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration. IEEE Transactions on CPMT 2 (8): 1229–1238.

    Google Scholar 

  28. Lau, J.H., C. Lee, C. Zhan, S. Wu, Y. Chao, M. Dai, R. Tain, H. Chien, J. Hung, C. Chien, R. Cheng, Y. Huang, Y. Lee, Z. Hsiao, W. Tsai, P. Chang, H. Fu, Y. Cheng, L. Liao, W. Lo, and M. Kao. 2014. Low-Cost Through-Silicon Hole Interposers for 3D IC Integration. IEEE Transactions on CPMT 4 (9): 1407–1419.

    Google Scholar 

  29. Hedler, H., T. Meyer, and B. Vasquez. 2001. Transfer wafer level packaging. US Patent 6,727,576, filed on October 31, 2001; patented on April 27, 2004.

    Google Scholar 

  30. Lau, J.H.. 2015. Patent Issues of Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 19 (November/December): 42–46.

    Google Scholar 

  31. Brunnbauer, M., E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi. 2006. An Embedded Device Technology Based on a Molded Reconfigured Wafer. In IEEE/ECTC Proceedings, 2006, 547–551.

    Google Scholar 

  32. Brunnbauer, M., E. Furgut, G. Beer, and T. Meyer. 2006. Embedded Wafer Level Ball Grid Array (eWLB). In IEEE/EPTC Proceedings, 2006, 1–5.

    Google Scholar 

  33. Keser, B., C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, and R. Wenzel. 2007. The Redistributed Chip Package: A Breakthrough for Advanced Packaging. In Proceedings of IEEE/ECTC, 2007, 286–291.

    Google Scholar 

  34. Kripesh, V., V. Rao, A. Kumar, G. Sharma, K. Houe, X. Zhang, K. Mong, N. Khan, and J.H. Lau. 2008. Design and Development of a Multi-Die Embedded Micro Wafer Level Package. In IEEE/ECTC Proceedings, 2008, 1544–1549.

    Google Scholar 

  35. Khong, C., A. Kumar, X. Zhang, S. Gaurav, S. Vempati, V. Kripesh, J.H. Lau, and D. Kwong. 2009. A Novel Method to Predict Die Shift During Compression Molding in Embedded Wafer Level Package. In IEEE/ECTC Proceedings, 2009, 535–541.

    Google Scholar 

  36. Sharma, G., S. Vempati, A. Kumar, N. Su, Y. Lim, K. Houe, S. Lim, V. Sekhar, R. Rajoo, V. Kripesh, and J.H. Lau. 2011. Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies. IEEE Transactions on CPMT 1 (5): 52–59.

    Google Scholar 

  37. Kumar, A., D. Xia, V. Sekhar, S. Lim, C. Keng, S. Gaurav, S. Vempati, V. Kripesh, J.H. Lau, and D. Kwong. 2009. Wafer Level Embedding Technology for 3D Wafer Level Embedded Package. In IEEE/ECTC Proceedings, 2009, 1289–1296.

    Google Scholar 

  38. Lim, Y., S. Vempati, N. Su, X. Xiao, J. Zhou, A. Kumar, P. Thaw, S. Gaurav, T. Lim, S. Liu, V. Kripesh, and J.H. Lau. 2010. Demonstration of High Quality and Low Loss Millimeter Wave Passives on Embedded Wafer Level Packaging Platform (EMWLP). IEEE Transactions on Advanced Packaging 33: 1061–1071.

    Article  Google Scholar 

  39. Lau, J.H., N. Fan, and M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20 (May/June): 38–44.

    Google Scholar 

  40. Kurita, Y., T. Kimura, K. Shibuya, H. Kobayashi, F. Kawashiro, N. Motohashi, and M. Kawano. 2010. Fan-Out Wafer-Level Packaging with Highly Flexible Design Capabilities. In IEEE/ESTC Proceedings, 2010, 1–6.

    Google Scholar 

  41. Motohashi, N., T. Kimura, K. Mineo, Y. Yamada, T. Nishiyama, K. Shibuya, H. Kobayashi, Y. Kurita, and M. Kawano. 2011. System in Wafer-Level Package Technology with RDL-First Process. In IEEE/ECTC Proceedings, 2011, 59–64.

    Google Scholar 

  42. Yoon, S., J. Caparas, Y. Lin, and P. Marimuthu. 2012. Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology. In IEEE/ECTC Proceedings, 2012, 1250–1254.

    Google Scholar 

  43. Tseng, C., C. Liu, C. Wu, and D. Yu. 2016. InFO (Wafer Level Integrated Fan-Out) Technology. In IEEE/ECTC Proceedings, 2016, 1–6.

    Google Scholar 

  44. Hsieh, C., C. Wu, and D. Yu. 2016. Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications. In IEEE/ECTC Proceedings, 2016, 1430–1438.

    Google Scholar 

  45. Yoon, S., P. Tang, R. Emigh, Y. Lin, P. Marimuthu, and R. Pendse. 2013. Fanout Flipchip eWLB (Embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions. In IEEE/ECTC Proceedings, 2013, 1855–1860.

    Google Scholar 

  46. Lin, Y., W. Lai, C. Kao, J. Lou, P. Yang, C. Wang, and C. Hseih. 2016. Wafer Warpage Experiments and Simulation for Fan-out Chip on Substrate. In IEEE/ECTC Proceedings, 2016, 13–18.

    Google Scholar 

  47. Chen, N., T. Hsieh, J. Jinn, P. Chang, F. Huang, J. Xiao, A. Chou, and B. Lin. 2016. A Novel System in Package with Fan-out WLP for high speed SERDES application. In IEEE/ECTC Proceedings, 2016, 1495–1501.

    Google Scholar 

  48. Chang, H., D. Chang, K. Liu, H. Hsu, R. Tai, H. Hunag, Y. Lai, C. Lu, C. Lin, and S. Chu. 2014. Development and 601 Characterization of New Generation Panel Fan-Out (PFO) Packaging Technology. In IEEE/ECTC Proceedings, 2014, 947–951.

    Google Scholar 

  49. Liu, H., Y. Liu, J. Ji, J. Liao, A. Chen, Y. Chen, N. Kao, and Y. Lai. 2014. Warpage Characterization of Panel Fab-out (P-FO) Package. In IEEE/ECTC Proceedings, 2014, 1750–1754.

    Google Scholar 

  50. Braun, T., S. Raatz, S. Voges, R. Kahle, V. Bader, J. Bauer, K. Becker, T. Thomas, R. Aschenbrenner, and K. Lang. 2015. Large Area Compression Molding for Fan-out Panel Level Packing. In IEEE/ECTC Proceedings, 2015, 1077–1083.

    Google Scholar 

  51. Che, F., D. Ho, M. Ding, X. Zhang. 2015. Modeling and Design Solutions to Overcome Warpage Challenge for Fanout Wafer Level Packaging (FO-WLP) Technology. In IEEE/EPTC Proceedings, 2015, 2–4.

    Google Scholar 

  52. Che, F., D. Ho, M. Ding, D. MinWoopp. 2016. Study on Process Induced Wafer Level Warpage of Fan-Out Wafer Level Packaging. In IEEE/ECTC Proceedings, 2016, 1879–1885.

    Google Scholar 

  53. Lau, J.H., M. Li, D. Tian, N. Fan, E. Kuah, K. Wu, M. Li, J. Hao, K. Cheung, L. Zhang, K. Tan, R. Beica, T. Taylor, C. Ko, H. Yang, Y. Chen, S. Lim, N. Lee, J. Ran, C. Xi, K. Wee, and Q. Yong. 2017. Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging. IEEE Transactions on CPMT, 1729–1738.

    Google Scholar 

  54. Kazama, A., T. Satoh, Y. Yamaguchi, I. Anjoh, and A. Nishimura. 2001. Development of Low-cost and Highly Reliable Wafer Process Package. In IEEE/ECTC Proceedings, May 2001, 40–46.

    Google Scholar 

  55. Wu, M., C. Liu, and D. Yu. 2016. UFI (UBM-Free Integration) Fan-In WLCSP Technology Enables Large Die Fine Pitch Packages. In IEEE/ECTC Proceedings, May 2016, 1154–1159.

    Google Scholar 

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Lau, J.H. (2018). Fan-in Wafer-Level Packaging Versus FOWLP. In: Fan-Out Wafer-Level Packaging. Springer, Singapore. https://doi.org/10.1007/978-981-10-8884-1_3

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  • DOI: https://doi.org/10.1007/978-981-10-8884-1_3

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  • Online ISBN: 978-981-10-8884-1

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