Design Integration and SOC Synthesis

Abstract

This chapter discusses about the SOC synthesis and the design partitioning. To have the better prototype of the SOC as we know that we can have the multiple FPGA architectures. Under such circumstances, the better design partitioning can result into the high performance to have the proof of concept. The chapter key focus is to address the important aspects while partitioning the design. How to overcome the partitioning challenges and how to use the synthesis, place and route, and STA tools with incremental approach to validate the complex SOC designs are also discussed in this chapter!

For the multiple FPGA prototypes, find the number of FPGAs using the initial gate estimation and by using the FPGA architecture.