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Design Space Exploration for Architectural Synthesis—A Survey

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Recent Findings in Intelligent Computing Techniques

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 708))

Abstract

Design Space Exploration (DSE) is the process of exploring design alternatives and it is iterative in nature. It includes a vast set of design choices and relies largely on the decision of the architect. The number of design constructs for a particular design is huge and it exponentially increases the problem complexity. To speed up the exploration process, many algorithms that find the optimal designs automatically have been proposed. This work presents a survey on the different techniques proposed to solve the Design Space Exploration problem by reducing the design space-time in order to provide good insight to researchers for further exploration.

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References

  1. Kritikakou, A., Catthoor, F., Goutis, C.: Scalable and Near-Optimal Design Space Exploration for Embedded Systems. Springer International Publishing (2014)

    Google Scholar 

  2. Mahapatra, A., Schafer, B.C.: Machine-learning based simulated annealer method for high level synthesis design space exploration. In: Proceedings of the Electronic System Level Synthesis Conference (ESLsyn). IEEE (2014)

    Google Scholar 

  3. Liu, D., Schafer, B.C.: Efficient and reliable high-level synthesis design space explorer for FPGAs. In: 26th International Conference on Field Programmable Logic and Applications (FPL), pp. 1–8 (2016)

    Google Scholar 

  4. Meng, P., Althoff, A., Gautier, Q., Kastner, R.: Adaptive threshold non-pareto elimination: re-thinking machine learning for system level design space exploration on FPGAs. In: Proceedings of Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 918–923 (2016)

    Google Scholar 

  5. Chen, T., Chen, Y., Guo, Q., Zhou, Z.H., Li, L., Xu, Z.: Effective and efficient microprocessor design space exploration using unlabeled design configurations. ACM Trans. Intell. Syst. Technol. (TIST) 5(1), 20 (2013)

    Article  Google Scholar 

  6. Chen, T., Guo, Q., Tang, K., Temam, O., Xu, Z., Zhou, Z.H., Chen, Y.: Archranker: a ranking approach to design space exploration. In: ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), pp. 85–96, June 2014

    Google Scholar 

  7. Liu, H.Y., Carloni, L.P.: On learning-based methods for design-space exploration with high-level synthesis. In: Proceedings of the 50th Annual Design Automation Conference, pp. 1–7, May 2013

    Google Scholar 

  8. Sinaei, S., Fatemi, O.: Novel heuristic mapping algorithms for design space exploration of multiprocessor embedded architectures. In: 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), pp. 801–804 (2016)

    Google Scholar 

  9. Carrion Schafer, B.: Probabilistic multiknob high-level synthesis design space exploration acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3), 394–406 (2016)

    Article  Google Scholar 

  10. da Silva, J.S., Bampi, S.: Area-oriented iterative method for design space exploration with high-level synthesis. In: 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), pp. 1–4 (2015)

    Google Scholar 

  11. Schafer, B.C.: Hierarchical high-level synthesis design space exploration with incremental exploration support. IEEE Embedded Syst. Lett. 7(2), 51–54 (2015)

    Article  Google Scholar 

  12. Sarkar, P., Sengupta, A., Naskar, M.K.: GA driven integrated exploration of loop unrolling factor and datapath for optimal scheduling of CDFGs during high level synthesis. In: 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 75–80 (2015)

    Google Scholar 

  13. Abdeen, H., Varró, D., Sahraoui, H., Nagy, A.S., Debreceni, C., Hegedüs, Á., Horvth, Á.: Multi-objective optimization in rule-based design space exploration. In: Proceedings of the 29th ACM/IEEE International Conference on Automated Software Engineering, pp. 289–300 (2014)

    Google Scholar 

  14. Sengupta, A., Mishra, V.K.: Integrated particle swarm optimization (i-PSO): an adaptive design space exploration framework for power-performance tradeoff in architectural synthesis. In: Fifteenth International Symposium on Quality Electronic Design, pp. 60–67 (2014)

    Google Scholar 

  15. Sengupta, A., Bhadauria, S.: Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm. In: IEEE 27th Canadian Conference on Electrical and Computer Engineering (CCECE), pp. 1–5 (2014)

    Google Scholar 

  16. Mishra, V.K., Sengupta, A.: MO-PSE: adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design. Adv. Eng. Softw. 67, 111–124 (2014)

    Article  Google Scholar 

  17. Sengupta, A., Mishra, V.K.: Swarm intelligence driven simultaneous adaptive exploration of datapath and loop unrolling factor during area-performance tradeoff. In: IEEE Computer Society Annual Symposium on VLSI, pp. 106–111 (2014)

    Google Scholar 

  18. Sengupta, A., Bhadauria, S.: Exploration of multi-objective tradeoff during high level synthesis using bacterial chemotaxis and dispersal. Elsevier J. Procedia Comput. Sci. 35, 63–72

    Article  Google Scholar 

  19. Sengupta, A., Bhadauria, S.: User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis. In: Sixteenth International Symposium on Quality Electronic Design, pp. 289–292 (2015)

    Google Scholar 

  20. Banzhaf, W., Nordin, P., Keller, R., Francone, F.: Genetic Programming—An Introduction. Morgan Kaufmann, San Francisco (1998)

    Google Scholar 

  21. Beni, G., Wang, J.: Swarm intelligence in cellular robotic systems, proceed. In: NATO Advanced Workshop on Robots and Biological Systems, Tuscany, Italy, June 2630 (1989)

    Google Scholar 

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Correspondence to R. Shathanaa .

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Shathanaa, R., Ramasubramanian, N. (2018). Design Space Exploration for Architectural Synthesis—A Survey. In: Sa, P., Bakshi, S., Hatzilygeroudis, I., Sahoo, M. (eds) Recent Findings in Intelligent Computing Techniques . Advances in Intelligent Systems and Computing, vol 708. Springer, Singapore. https://doi.org/10.1007/978-981-10-8636-6_55

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  • DOI: https://doi.org/10.1007/978-981-10-8636-6_55

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-8635-9

  • Online ISBN: 978-981-10-8636-6

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