Abstract
Performance of flash ADCs is beset in presence of offsets in comparators. Offsets present in comparators of a flash ADC give rise to bubble or sparkle error. There are several methods to eliminate this error—both first order or higher ones. In this paper, performance evaluation of flash ADCs will be carried out using hot code generator and bit swap logic (BSL) in presence of such offsets. It is well known that while hot code generators can take care of only first-order error in the thermometric code, BSL method can take care of any order of error. Simulation for a 3-bit flash ADC has been carried out in the presence of offsets and it has been shown that while the hot code generator can get rid of only first-order error, the BSL method overcomes any order of error.
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References
Kharate, G.K.: Digital Electronics. Oxford University Press (2012)
Daegyu, L., Cheol, Y.J., Kyusun, C., Ghaznavi, J.: Fat tree encoder design for ultra-high speed flash A/D converters, circuits and systems. In: the 45th Midwest Symposium, pp. 87–90 (2002)
Agarwal, N., Paily, R.: An improved ROM architecture for bubble error suppression in high speed flash ADCs. In: Proceedings of AISPC, pp. 1–5 (2008)
Uyttenhove, K., Marques, A., Steyaert, M.: A 6-bit 1 GHz acquisition speed CMOS flash ADC with digital error correction. In: Proceedings of the IEEE Conference, pp. 249–252 (2000)
Mangelsdorf, C.: A 400-MHz input flash converter with error correction. IEEE J. Solid-State Circuits 25(1), 184–191 (1990)
Hieu, B.V., Choi, S., Seon, J., Oh, Y., Park, C., Park, J., Kim, H., Jeong, T.: A new approach to thermometer to binary encoder of flash ADCS—bubble error detection circuits. IEEE MWSCAS 5–8 (2011)
Hieu, B.V., Beak, S., Choi, S., Seon, J., Jeong, T.T.: Thermometer to binary encoder with bubble error correction (BEC) circuit for flash analog to digital converter (FADC). In: 3rd International Conference on Communications and Electronics (ICCE), pp. 102–106 (2010)
Wallace, C.S.: A suggestion for a fast multiplier. IEEE Trans. Electron. Comput. 13(1), 14–17 (1964)
Garuts, V.E., Simon Yu, Y-C., Traa, E.O., Yamaguchi, T.: A Dual 4-bit 2-Gs/S full nyquist analog-to-digital converterusing a 70-ps silicon bipolar technology with borosenic-poly process and coupling-base implant. IEEE J. Solid-State Circuits 24 (2), 216-222 (1989)
Pereira, P., Fernande, J.R.: Comparative study of encoders for parallel type ADCS. In: 6th Euro Workshop on ADC Modelling and Testing, pp. 142–146 (2001)
Ghoshal, P., Sen, S.K.: A bit swap logic (BSL) based bubble error correction (BEC) method for flash ADCs. In: International Conference on Control, Instrumentation, Energy and Communication, CIEC-16, Jan 30–Feb 01, pp. 111–115 (2016)
Analysis of Non-ideal Effects of Pipelined ADC by Using MATLAB–Simulink, Advances in Sensors, Signals and Materials, pp. 85–88, ISSN: 1792-6211/ISSN: 1792-6238
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Ghoshal, P., Sen, S.K. (2018). Performance Evaluation of Flash ADCs in Presence of Offsets Using Hot Code Generator and Bit Swap Logic (BSL). In: Bhattacharyya, S., Sen, S., Dutta, M., Biswas, P., Chattopadhyay, H. (eds) Industry Interactive Innovations in Science, Engineering and Technology . Lecture Notes in Networks and Systems, vol 11. Springer, Singapore. https://doi.org/10.1007/978-981-10-3953-9_42
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DOI: https://doi.org/10.1007/978-981-10-3953-9_42
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