Abstract
Due to plenty of intrinsic overheads in synchronous circuit design, asynchronous designs have drawn consideration in the Electronic Design Automation Industry. In an asynchronous logic design methodologies, Null Convention Logic is the best delay-insensitive logic as it has many advantages such as inherent robustness, power consumption, and modular reusability. For digital signal processing and computational dynamic range applications, floating point multiplication is a critical part with high precision and low power. Null cycle reduction technique and fine grain pipelining can be applied to the Null Convention Logic floating point multiplier to increase throughput. In this paper, Multiplier using Asynchronous Delay-Insensitive single precision NCL Floating Point Multiplier with IEEE-754 standard architecture is proposed and its performance is compared with different topologies in terms of various metrics such as delay, area, power consumption, and percentage of energy savings.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Smith SC, Di J (2009) Designing asynchronous circuits using NULL convention logic. Synth Lect Digit Circuits Syst 4(1):1–96
Fant KM (2005) Logically determined design: clockless system design with null convention logic. Wiley, Hoboken
Bandapati SK, Smith SC (2007) Design and characterization of NULL convention arithmetic logic units. Microelectron Eng 84(2):280
Parsan FA, Smith SC (2012) CMOS implementation of static threshold gates with hysteresis. In: Proceedings of the IEEE/IFIP 20th international conference on VLSI and system-on-chip(VLSI-SoC ’12), pp 41–45
Song Z, Smith SC (2013) Implementation of a fast fourier transform processor in NULL convention logic. In: Proceedings of the international conference on computer design, pp 10–16
Kotipalli S, Kim Y-B, Choi M (2014) Asynchronous advanced encryption standard hardware with random noise injection for improved side-channel attack resistance. J Electr Comput Eng 2014(837572):13–15
Smith SC (2007) Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits. IEEE Trans Very Large Scale Integr VLSI Syst 15(6):672–683
Reese RB, Smith SC, Thornton MA (2012) Uncle: an RTL approach to asynchronous design. In: Proceedings of the 18th IEEE international symposium on asynchronous circuits and systems (ASYNC ’12), Lyngby, pp 65–72
Bandapati SK, Smith SC, Choi M (2003) Design and characterization of NULL convention self-timed multipliers. IEEE Des Test Comput 20(6):26–36
Smith CM, Smith SC (2010) Comparison of NULL convention booth multipliers. In: Proceedings of the international conference on computer design (CDES ’10), pp 3–9
Sankar R, Kadiyala V, Bonam R (2007) Implementation of static and semi-static versions of a bit-wise pipelined dual-rail NCL 2s complement multiplier. In: Proceedings of the IEEE region 5 technical conference (TPS ’07), pp 228–233
Men L, Di J (2014) An asynchronous finite impulse response filter design for digital signal processing circuit. In: Proceedings of the IEEE 57th international midwest symposium on circuits and systems (MWSCAS ’14), College Station, pp 25–28
Al-Ashrafy M, Salem A, Anis W (2011) An efficient implementation of floating point multiplier. In: Proceedings of the Saudi international electronics, communications and photonics conference (SIECPC ’11), pp 1–5
Parhi KK (2007) VLSI digital signal processing systems-design and implementation. Wiley, New York
Weste N, Harris D (2011) CMOS VLSI design: a circuits and systems perspective, 4th edn. Addison-Wesley, Boston
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Sudhakar, J., Alekhya, Y., Syamala, K.S. (2018). A Dual-Rail Delay-Insensitive IEEE-754 Single-Precision Null Convention Floating Point Multiplier for Low-Power Applications. In: Saini, H., Singh, R., Reddy, K. (eds) Innovations in Electronics and Communication Engineering . Lecture Notes in Networks and Systems, vol 7. Springer, Singapore. https://doi.org/10.1007/978-981-10-3812-9_13
Download citation
DOI: https://doi.org/10.1007/978-981-10-3812-9_13
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-3811-2
Online ISBN: 978-981-10-3812-9
eBook Packages: EngineeringEngineering (R0)