Combinational Logic Design Using VHDL Constructs

Abstract

This chapter discusses the RTL coding and synthesis using VHDL for the key combinational arithmetic resources such as adders, subtractors, multipliers, and comparators. This chapter is useful for the beginners to understand about the use of the concurrent and sequential VHDL constructs such as process, if then else, case, and their use in the design of combinational logic. Even this chapter discusses the code converters, data selectors as multiplexers, decoders, and encoders. This chapter is organized in such a way that it covers simple logic design and gate delay concepts to the priority logic design. This chapter concludes with the summary.

The original version of this chapter was revised: The incorrect information have been corrected. The erratum to this chapter is available at 10.1007/978-981-10-3296-7_12