Skip to main content
SpringerLink
Log in

ASiPEC: An Application Specific Instruction-Set Processor for High Performance Entropy Coding

  • Conference paper
  • First Online:
Ubiquitous Computing Application and Wireless Sensor

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 331))

  • 1576 Accesses

Abstract

Entropy coding becomes a performance bottle neck in video codecs because it requires a large amount of bitwise computation. Many video systems accelerate the coding process by implementing it as a hardwired accelerator or by executing it on an extra general-purpose processor to meet performance requirement. However, the variety of video formats causes a high degree of complication to a hardwired accelerator, which increases implementation cost and complexity. When an extra processor is used for the coding process, the property of using variable-length operands in the coding process significantly causes computation inefficiency. This paper presents a novel processor architecture which provides an instruction set suitable for efficient execution of entropy coding process as well as supports for multiple video formats.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 169.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 219.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. Alle M, Biswas J, Nandy SK (2006) High performance VLSI architecture design for H.264 CAVLC decoder. In: International conference on application-specific systems, architectures and processors, pp. 317–322

    Google Scholar 

  2. Han JH, Lee MY, Bae Y, Cho H (2005) Application specific processor design for H. 264 decoder with a configurable embedded processor. ETRI J 27(5):491–496

    Article  Google Scholar 

  3. Jo HH, Seo JH, Sim DG, Kim DH, Song JH, Kim D, Lee S (2013) Bitstream parsing processor with emulation prevention bytes removal for H.264/AVC decoder. In: IEEE international conference of consumer electronics, pp. 27–28

    Google Scholar 

  4. Kim KW, Park SH, Paek YH (2009) Application-specific instruction set processor for H.264 on-chip encoder. ISOCC, pp. 373–376

    Google Scholar 

  5. Kim SD, Sunwoo MH (2008) ASIP approach for implementation of H. 264/AVC. J Sign Proces Syst 50(1):53–67

    Article  Google Scholar 

  6. Lee BY, Ryoo KK (2010) A design of high-performance pipelined architecture for H.264/AVC CAVLC decoder and low-power implementation. IEEE Trans Consum Electron 56(4):2781–2789

    Article  Google Scholar 

  7. Lee JJ, Park SM, Eum, NW (2008) Design of application specific processor for H.264 inverse transform and quantization. ISOCC, II.57–II.60

    Google Scholar 

  8. Seo JH, Jo HH, Sim DG, Kim DH, Song JH (2013) Fast CAVLD of H.264 on bitstream decoding processor. EURASIP J Image Video Process 2013(1):23

    Google Scholar 

  9. Sohm O (2002) Variable-length decoding on the TMS320C6000 DSP platform. Application report TMS320C6000 DSP platform, Texas Instruments

    Google Scholar 

  10. Song JH, Lee WC, Kim DH, Kim D (2012) Low power video decoding system using a reconfigurable processor. In: IEEE international conference of consumer electronics, pp. 532–533

    Google Scholar 

  11. Tsai TH, Fang TL, Pan YN (2011) A Novel design of CAVLC decoder with low power and high throughput considerations. IEEE Trans Circuits Syst Video Technol 21(3):311–319

    Article  Google Scholar 

  12. Werda I, Kossentini F, Ayed B, Massmoudi N (2006) Analysis and optimization of UB Video’s H.264 baseline encoder implementation on texas instruments’ TMS320DM642 DSP. In: International conference on image processing, pp. 3277–3280

    Google Scholar 

Download references

Acknowledgments

This chapter is based upon work supported by the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the ITRC (Information Technology Research Center) support program supervised by the NIPA (National IT Industry Promotion Agency)” (NIPA-2014-H0301-14-1018).

Author information

Authors and Affiliations

  1. Department of Computer Engineering, Kwangwoon University, Seoul, 139-701, Korea

    Seung-Hyun Choi & Seong-Won Lee

  2. Department of Computer Science and Engineering, Konkuk University, Seoul, 143-701, Korea

    Neungsoo Park

  3. Department of Electronics and Computer Engineering, Hanyang University, Seoul, 133-791, Korea

    Yong Ho Song

Authors
  1. Seung-Hyun Choi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Neungsoo Park
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Yong Ho Song
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Seong-Won Lee
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Seong-Won Lee .

Editor information

Editors and Affiliations

  1. Computer Science and Engineering, Seoul National University of Science & Technology SeoulTech, Seoul, Korea, Republic of (South Korea)

    James J. (Jong Hyuk) Park

  2. Department of Computer Science, Georgia State University, Atlanta, Georgia, USA

    Yi Pan

  3. President, National Ilan University, Yilan City, Taiwan

    Han-Chieh Chao

  4. Computer Science & Engineering, Gangneung-Wonju Natioanl University, Wonju, Korea, Republic of (South Korea)

    Gangman Yi

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer Science+Business Media Dordrecht

About this paper

Cite this paper

Choi, SH., Park, N., Song, Y.H., Lee, SW. (2015). ASiPEC: An Application Specific Instruction-Set Processor for High Performance Entropy Coding. In: Park, J., Pan, Y., Chao, HC., Yi, G. (eds) Ubiquitous Computing Application and Wireless Sensor. Lecture Notes in Electrical Engineering, vol 331. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-9618-7_7

Download citation

  • DOI: https://doi.org/10.1007/978-94-017-9618-7_7

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-017-9617-0

  • Online ISBN: 978-94-017-9618-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation