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Future Trend in Adiabatic Logic

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Adiabatic Logic

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 34))

Abstract

Scaling of CMOS devices has a strong impact on transistors and, thus, also on the operation of Adiabatic Logic. The impact of scaling is estimated by means of simulation of industrial and predictive technology models and a trend for scaling down to the 16 nm node is presented. Revolutionary transistor concepts like the Carbon Nanotube Transistor and the Vertical Slit Field Effect Transistor show promising properties. The impact of those new devices on Adiabatic Logic is explained. Besides favorable properties also unwanted effects accompany the miniaturization of the devices in the nanometer regime. Stress effects like Hot-Carrier Injection and the Bias Temperature Instability degrade the device performance continuously. The outcome of the worsening of the devices is rated for Adiabatic Logic and a comparison to static CMOS is stated.

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Bibliography

  1. W.P. Maly, Integrated circuit, device, system, and method of fabrication. US Patent PCT/US2007/011630, 2007

    Google Scholar 

  2. E. Amirante, Adiabatic Logic in Sub-quartermicron CMOS Technologies. Selected Topics of Electronics and Micromechatronics, vol. 13 (Shaker, Aachen, 2004)

    Google Scholar 

  3. J. Fischer, Adiabatische Schaltungen und Systeme in Deep-Submicron-CMOS-Technologien. Selected Topics of Electronics and Micromechatronics, vol. 24 (Shaker, Aachen, 2006)

    Google Scholar 

  4. S. Nakata, The stability of adiabatic reversible logic using asymmetric tank capacitors and its application to SRAM. IEICE Electron. Express 2(20), 512–518 (2005)

    Article  Google Scholar 

  5. G.E. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 114–117 (1965)

    Google Scholar 

  6. D. Hecht, Properties and applications of carbon nanotube films: a revolutionary material for transparent and flexible electronics, PhD thesis, University of California Los Angeles, 2007

    Google Scholar 

  7. P. Avouris, J. Appenzeller, V. Derycke, R. Martel, S. Wind, Carbon nanotube electronics, in Digest. International Electron Devices Meeting, 2002, pp. 281–284

    Chapter  Google Scholar 

  8. P. Avouris, J. Appenzeller, R. Martel, S.J. Wind, Carbon nanotube electronics. Proc. IEEE 91(11), 1772–1784 (2003)

    Article  Google Scholar 

  9. J. Appenzeller, J. Knoch, R. Martel, V. Derycke, S.J. Wind, P. Avouris, Carbon nanotube electronics. IEEE Trans. Nanotechnol. 1(4), 184–189 (2002)

    Article  ADS  Google Scholar 

  10. A. Javey, J. Guo, Q. Wang, M. Lundstrom, H. Dai, Ballistic carbon nanotube field-effect transistors. Nature 424(6949), 654–657 (2003)

    Article  ADS  Google Scholar 

  11. C. Hu, S.C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, K.W. Terrill, Hot-electron-induced MOSFET degradation model, monitor, and improvement. IEEE Trans. Electron Devices 32(2), 375–385 (1985)

    Article  ADS  Google Scholar 

  12. K.O. Jeppson, C.M. Svensson, Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices. J. Appl. Phys. 48(5), 2004–2014 (1977)

    Article  ADS  Google Scholar 

  13. G. Bersuker, J. Sim, C.S. Park, C. Young, S. Nadkarni, R. Choi, B.H. Lee, Mechanism of electron trapping and characteristics of traps in HfO2 gate stacks. IEEE Trans. Device Mater. Reliab. 7(1), 138–145 (2007)

    Article  Google Scholar 

  14. S. Pae, M. Agostinelli, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Kavalieros, K. Kuhn, M. Kuhn, J. Maiz, M. Metz, K. Mistry, C. Prasad, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, J. Thomas, C. Wiegand, J. Wiedemer, BTI reliability of 45 nm high-K + metal-gate process technology, in IEEE International Reliability Physics Symposium, 2008, pp. 352–357

    Chapter  Google Scholar 

  15. C. Schluender, R. Brederlow, P. Wieczorek, C. Dahl, J. Holz, M. Roehner, S. Kessel, V. Herold, K. Goser, W. Weber, R. Thewes, Trapping mechanisms in negative bias temperature stressed p-MOSFETs. Microelectron. Reliab. 39(6–7), 821–826 (1999)

    Google Scholar 

  16. C. Schlueunder, W. Heinrigs, W. Gustin, H. Reisinger, On the impact of the NBTI recovery phenomenon on lifetime prediction of modern p-MOSFETs, in IEEE International Integrated Reliability Workshop (Final Report), 2006, pp. 1–4

    Chapter  Google Scholar 

  17. V. Huard, C. Parthasarathy, N. Rallet, C. Guerin, M. Mammase, D. Barge, C. Ouvrard, New characterization and modeling approach for NBTI degradation from transistor to product level, in IEEE International Electron Devices Meeting, 2007, pp. 797–800

    Chapter  Google Scholar 

  18. V. Huard, C.R. Parthasarathy, A. Bravaix, T. Hugel, C. Guerin, E. Vincent, Design-in-reliability approach for NBTI and hot-carrier degradations in advanced nodes. IEEE Trans. Device Mater. Reliab. 7(4), 558–570 (2007)

    Article  Google Scholar 

  19. International technology roadmap for semiconductors—2008 update, http://www.itrs.net/Links/2008ITRS/Home2008.htm

  20. Y. Cao, T. Sato, M. Orshansky, D. Sylvester, C. Hu, New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation, in Proc. of the IEEE Custom Integrated Circuits Conference, 2000, pp. 201–204

    Google Scholar 

  21. W. Zhao, Y. Cao, New generation of predictive technology model for sub-45nm design exploration, in Proc. 7th International Symposium on Quality Electronic Design, 2006, pp. 585–590

    Chapter  Google Scholar 

  22. Arizona state university predictive technology model, http://www.eas.asu.edu/~ptm/

  23. International technology roadmap for semiconductors—2009 edition (2009), http://www.itrs.net/Links/2009ITRS/Home2009.htm

  24. R. Chau, S. Datta, A. Majumdar, Opportunities and challenges of III–V nanoelectronics for future high-speed, low-power logic applications, in IEEE Compound Semiconductor Integrated Circuit Symposium, 2005

    Google Scholar 

  25. P. Teichmann, J. Fischer, E. Amirante, S. Henzler, A. Bargagli-Stoffi, C. Otte, D. Schmitt-Landsiedel, Gate leakage reduction by clocked power supply of adiabatic logic circuits. Adv. Radio Sci. 3(14), 281–285 (2005)

    Article  ADS  Google Scholar 

  26. N. Hamada, S.-i. Sawada, A. Oshiyama, New one-dimensional conductors: Graphitic microtubules. Phys. Rev. Lett. 68(10), 1579–1581 (1992)

    Article  ADS  Google Scholar 

  27. A. Javey, H. Dai, Carbon nanotube electronics, in 19th International Conference on VLSI Design, 2006

    Google Scholar 

  28. R. Martel, V. Derycke, C. Lavoie, J. Appenzeller, K.K. Chan, J. Tersoff, P. Avouris, Ambipolar electrical transport in semiconducting single-wall carbon nanotubes. Phys. Rev. Lett. 87(25), 256805 (2001)

    Article  ADS  Google Scholar 

  29. A. Raychowdhury, K. Roy, Carbon nanotube electronics: Design of high-performance and low-power digital circuits. IEEE Trans. Circuits Syst. I 54(11), 2391–2401 (2007)

    Article  Google Scholar 

  30. V. Derycke, R. Martel, J. Appenzeller, P. Avouris, Carbon nanotube inter- and intramolecular logic gates. Nano Lett. 1(9), 453–456 (2001)

    Article  ADS  Google Scholar 

  31. J. Deng, A. Lin, G.C. Wan, H.-S.P. Wong, Carbon nanotube transistor compact model for circuit design and performance optimization. J. Emerg. Technol. Comput. Syst. 4(2), 1–20 (2008)

    Article  Google Scholar 

  32. J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its applications, Part I: Model of the intrinsic channel region. IEEE Trans. Electron Devices 54(12), 3186–3194 (2007)

    Article  ADS  Google Scholar 

  33. J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its applications, Part II: Full device model and circuit performance benchmarking. IEEE Trans. Electron Devices 54(12), 3195–3205 (2007)

    Article  ADS  Google Scholar 

  34. P.A. Mildred, S. Dresselhaus, G. Dresselhaus (eds.), Carbon Nanotubes: Synthesis, Structure, Properties, and Applications (Springer, Berlin, 2001)

    Google Scholar 

  35. J.M. Marulanda, Current transport modeling of carbon nanotubes: Concepts, analysis, and design, PhD thesis, Louisiana State University, 2008

    Google Scholar 

  36. M. Weis, A circuit design perspective for vertical slit field effect transistor (VESFET), in Selected Topics of Electronics and Micromechatronics, vol. 35 (Shaker, Aachen, 2010)

    Google Scholar 

  37. Y.-W. Lin, M. Marek-Sadowska, W. Maly, A. Pfitzner, D. Kasprowicz, Is there always performance overhead for regular fabric? in Proc. IEEE International Conference on Computer Design, 2008, pp. 557–562

    Chapter  Google Scholar 

  38. Y. Miura, Y. Matukura, Investigation of silicon-silicon dioxide interface using MOS structure. Jpn. J. Appl. Phys. 5, 180 (1966)

    Article  ADS  Google Scholar 

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  1. Lehrstuhl für Technische Elektronik, Technische Universität München, Arcisstrasse 21, 80333, Munich, Germany

    Dr.-Ing. Philip Teichmann

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  1. Dr.-Ing. Philip Teichmann
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Teichmann, P. (2012). Future Trend in Adiabatic Logic. In: Adiabatic Logic. Springer Series in Advanced Microelectronics, vol 34. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2345-0_3

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  • DOI: https://doi.org/10.1007/978-94-007-2345-0_3

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-2344-3

  • Online ISBN: 978-94-007-2345-0

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