Abstract
This chapter discusses the advancements made in SAR ADCs for wireless applications, which require accuracies in the range of 8–10 bit and a few 10’s of MHz sampling speed. An overview is given of recent techniques that reduce the switching power in the capacitive DAC, and as such improve the power efficiency of the ADC up to levels that are out of reach of the typically used pipeline architecture.
The second part of this paper discusses the charge-sharing SAR ADC architecture, which proposes a new signal processing method in the charge domain that removes the often-neglected though requirements for the reference buffer. An implementation in 40 nm CMOS achieves 9.3ENOB and 60MS/s at a figure of merit of 34 fJ.
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Acknowledgment
The work presented here is the result of the research on ADCs performed in imec’s wireless research group in the past years, and the author would like to acknowledge the contributions of all team members, an especially Vito Giannini, Geert van der Plas, Bob Verbruggen, and Takaya Yamamoto.
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Craninckx, J. (2012). Low-Power Successive Approximation ADCS for Wireless Applications. In: Steyaert, M., van Roermund, A., Baschirotto, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1926-2_3
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DOI: https://doi.org/10.1007/978-94-007-1926-2_3
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