Abstract
Given the increasing complexity of Chip Multi-Processors (CMPs), a wide range of architecture parameters must be explored at design time to find the best trade-off in terms of multiple competing objectives (such as energy, delay, bandwidth, area, etc.) The design space of the target architectures is huge because it should consider all possible combinations of each hardware parameter (e.g., number of processors, processor issue width, L1 and L2 cache sizes, etc.). In this complex scenario, intuition and past experience of design architects is no more a sufficient condition to converge to an optimal design of the system. Indeed, Automatic Design Space Exploration (DSE) is needed to systematically support the analysis and quantitative comparison of a large amount of design alternatives in terms of multiple competing objectives (by means of Pareto analysis). The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures .
This project is supported by the EC under grant MULTICUBE FP7-216693.
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Notes
- 1.
CoWare is now a part of Synopsys Inc.
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Acknowledgements
We would like to gratefully acknowledge our EC Project Officer, Panagiotis Tsarchopoulos and our reviewers: Alain Perbost, Andrzej Pulka and Kamiar Sehat for their valuable comments and guidance during the project review process.
Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman and Maryse Wouters are also associated with Interdisciplinary Institute for BroadBand Technology, Belgium (IBBT), B-9050 Gent, Belgium.
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Silvano, C. et al. (2011). MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_4
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