Skip to main content
SpringerLink
Log in

Decoder Logic Design

  • Chapter
  • First Online:
Regular Nanofabrics in Emerging Technologies

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 82))

  • 538 Accesses

Abstract

Among the different emerging technologies surveyed previously in Chap. 1, crossbars are a very promising approach to integrate silicon nanowires and molecular switches into functional circuits. Chapter 2 proposed a fabrication framework for crossbars, the multi-spacer patterning technique, which has the advantage of being CMOS compatible and using only photolithography steps. Other approaches to fabricate crossbars reported in literature include nanomolds and self-assembly.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Notes

  1. 1.

    If we consider short channel transistors, then the saturation current is proportional to \((V_{{\rm A},i}-V_{\rm T})\) and \(\delta=(\alpha+\upsilon)/q\)

References

  1. DeHon A, Lincoln P, Savage J (2003) Stochastic assembly of sublithographic nanoscale interfaces. IEEE Trans Nanotechnol 2(3):165–174

    Article  Google Scholar 

  2. Savage JE, Rachlin E, DeHon A, Lieber CM, Wu Y (2006) Radial addressing of nanowires. ACM J Emerg Technol Comput Syst 2(2):129–154

    Article  Google Scholar 

  3. Kuekes PJ, Williams RS (2001) Demultiplexer for a molecular wire crossbar network (MWCN DEMUX). US Patent 6,256,767, 2001

    Google Scholar 

  4. Hogg T, Chen Y, Kuekes P (2006) Assembling nanoscale circuits with randomized connections. IEEE Trans Nanotechnol 5(2):110–122

    Article  Google Scholar 

  5. Gopalakrishnan K, Shenoy RS, Rettner C, King R, Zhang Y, Kurdi B, Bozano LD, Weslser JJ, Rothwell MB, Jurich M, Sanchez MI, Hernandez M, Rice PM, Risk WP, Wickramasinghe HK (2005) The micro to nano addressing block. In: IEEE Electron Devices Meeting, p. 19.4

    Google Scholar 

  6. Ben Jamaa MH, Atienza D, Moselund KE, Bouvet D, Ionescu AM, Leblebici Y, De Micheli G (2008) Variability-aware design of multi-level logic decoders for nanoscale crossbar memories. IEEE Trans Computer-Aided Des 27(11):2053–2067

    Article  Google Scholar 

  7. Ben Jamaa MH, Leblebici Y, De Micheli G (2009) Decoding nanowire arrays fabricated with the multi-spacer patterning technique. In: Design Automation Conference (DAC), July 2009, San Francisco, California, USA

    Google Scholar 

  8. Luo Y, Collier CP, Jeppesen JO, Nielsen KA, DeIonno E, Ho G, Perkins J, Tseng H-R, Yamamoto T, Stoddart JF, Heath JR (2002) Two-dimensional molecular electronics circuits. J Chem Phys Phys Chem 3:519–525

    Article  Google Scholar 

  9. DeHon A (2005) Design of programmable interconnect for sublithographic programmable logic arrays. In: Proceedings of the International Symposium on Field-Programmable Gate Arrays (FPGA), pp 127–137

    Google Scholar 

  10. Beckman R, Johnston-Halperin E, Luo Y, Green JE, Heath JR (2005) Bridging dimensions: demultiplexing ultrahigh density nanowire circuits. Science 310(5747):465–468

    Article  Google Scholar 

  11. Anderson DA, Metze G (1995) Design of totally self-checking check circuits for m-out of-n codes. In: Twenty-Fifth International Symposium on Fault-Tolerant Computing Highlights from Twenty-Five Years, pp 244– 248, 27–30 June 1995

    Google Scholar 

  12. Gardner M (1972) The curious properties of the Gray code and how it can be used to solve puzzles. Sci Am 227:106–109

    Article  Google Scholar 

  13. Gray F (1953) Pulse code communication. US Patent No. 2632058, 1953

    Google Scholar 

  14. Bhat GS, Savage CD (1996) Balanced Gray codes. Electron J Comb 3(1):R25

    Google Scholar 

  15. Smith KC (1981) The prospects for multivalued logic: a technology and applications view. IEEE Trans Comput 30(9):619–634

    Article  MathSciNet  MATH  Google Scholar 

  16. Smith KC (1988) Multiple valued logic: a tutorial and appreciation. Computer 21(4):17–27

    Article  Google Scholar 

  17. Current K (1994) Current-mode CMOS multiple-valued logic circuits. IEEE J Solid-State Circuits 29(2):95–107

    Article  Google Scholar 

  18. Ogawa K, Shibata T, Ohmi T, Takatsu M, Yokoyama N (1998) Multiple-input neuron MOS operational amplifier for voltage-mode multivalued full adders. IEEE Trans Circuits Systems II: Analog Digit Signal Process 45(9):1307–1311

    Article  Google Scholar 

  19. Kencke D, Richart R, Garg S, Banerjee S (1998) A multilevel approach toward quadrupling the density of ash memory. IEEE Electron Device Lett 19(3):86–88

    Article  Google Scholar 

  20. Mahapatra S, Ionescu AM (2005) Realization of multiple valued logic and memory by yybrid SETMOS architecture. IEEE Trans Nanotechnol 4(6):705–714

    Article  Google Scholar 

  21. Miller D (1993) Multiple-valued logic design tools. In: Proceedings of the 23rd IEEE International Symposium on Multiple Valued Logic, Sacramento, California, USA, pp 2–11, 24–27 May 1993

    Google Scholar 

  22. Sasao T (1989) On the optimal design of multiple-valued PLAs. IEEE Trans Comput 38(4):582–592

    Article  MathSciNet  MATH  Google Scholar 

  23. Rudell R, Sangiovanni-Vincentelli A (1987) Multiple-valued minimization for PLA optimization. IEEE Trans Computer-Aided Des Integr Circuits Syst 6(5):727–750

    Article  Google Scholar 

  24. Sasao T (1993) EXMIN2: A simplification algorithm for exclusive-OR-sumof- products expressions for multiple-valued-input two-valued-output functions. IEEE Trans Computer-Aided Des 12(5):621–632

    Article  Google Scholar 

  25. Song N, Perkowski M (1996) Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions. IEEE Trans Computer-Aided Des Integr Circuits Syst 15(4):385–395

    Article  Google Scholar 

  26. Files C, Perkowski M (2000) New multivalued functional decomposition algorithms based on MDDs. IEEE Trans Computer-Aided Des Integr Circuits Syst 19(9):1081–1086

    Article  Google Scholar 

  27. Jiang Y, Brayton R (2000) Don’t cares and multi-valued logic network minimization. In: IEEE/ACM International Conference on Computer Aided Design, 2000. ICCAD-2000, pp 520–525

    Google Scholar 

  28. Rachlin E (2006) Robust nanowire decoding. http://www.cs.brown.edu/publications/theses/masters/2006/eerac.pdf 2006

  29. International technology roadmap for semiconductors (ITRS) (2007) http://www.itrs.net/reports.html. Tech. Rep., 2007

  30. Moselund KE, Bouvet D, Ben Jamaa HH, Atienza D, Leblebici Y, De Micheli G, Ionescu AM (2008) Prospects for logic-on-a-wire. Microelectron Eng 85:1406–1409

    Article  Google Scholar 

  31. Sze SM, Ng KK (2007) Physics of semiconductor devices. Wiley-Interscience, New Jersy

    Google Scholar 

  32. Cristoloveanu S (1995) Electrical characterization of silicon-on-insultaor materials and devices. Springer, Heidelberg

    Book  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Commissariat à l’Energie Atomique (CEA-L DRT-LETI-DACLE-LISAN), Rue des Martyrs 17, 38054, Grenoble, France

    M. Haykel Ben Jamaa

Authors
  1. M. Haykel Ben Jamaa
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to M. Haykel Ben Jamaa .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Ben Jamaa, M.H. (2011). Decoder Logic Design. In: Regular Nanofabrics in Emerging Technologies. Lecture Notes in Electrical Engineering, vol 82. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-0650-7_3

Download citation

  • DOI: https://doi.org/10.1007/978-94-007-0650-7_3

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-0649-1

  • Online ISBN: 978-94-007-0650-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation