Efficient-Fused Architectures for FFT Processor Using Floating-Point Arithmetic

Abstract

In this chapter, the complex multiplier is designed using the fused dot product architecture. The floating-point number is used in this implementation for its wider range and its applications requiring the data space range from small to infinitely large. For the digital applications, the adder, subtractor, and multiplier are required at same instance. The discrete way of implementing the dot product yielded more space (in parallel implementation), high latency (in serial implementation), and power consumption. Hence, the research in fusing of the arithmetic units such as floating-point adder, subtractor, and multiplier gained interest. With the fused dot product unit, the output can be obtained in a single clock with low area and minimum latency. To further improve the performance of the fused dot product (FDP), the optimization in the architecture had been carried out and the result has been discussed. Further, the FDP unit is implemented in the complex multiplier. Thus, the performance of complex multiplier in FFT is improved and the error in computation is reduced. This optimized fused architecture can also be used in implementation in the processors and other such systems.