Abstract
In this paper, the design of low-power, high-speed, two-stage, indirect frequency-compensated operational amplifier is presented. The OPAMP employs split-length devices and class AB output stage. Split-length technique is employed both in load device as well as in differential-pair device. The split-length device enhances the phase margin (PM) and unity gain bandwidth (UGB) while maintaining lower supply voltage. The class AB output stage provides a faster settling time and reduced power dissipation. Simulations of the proposed circuits were carried out in cadence specter on 180-nm process technology at a supply voltage of 1.6 V. The proposed split-length current mirror load OPAMP exhibits power dissipation of 82 µW, UGB of 43.26 MHz, and PM of 79.25°. Similarly, the proposed split-length differential-pair OPAMP exhibits a power dissipation of 78 µW, UGB of 49.71 MHz, and PM of 85.34°.
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Das, S., Mandal, S.K., Rath, A., Dash, S.P. (2015). Low-Power, High-Speed, Indirect Frequency-Compensated OPAMP with Class AB Output Stage in 180-nm CMOS Process Technology. In: Jain, L., Patnaik, S., Ichalkaranje, N. (eds) Intelligent Computing, Communication and Devices. Advances in Intelligent Systems and Computing, vol 308. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2012-1_49
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DOI: https://doi.org/10.1007/978-81-322-2012-1_49
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