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Modeling Hot-Carrier Effects

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MOSFET Models for VLSI Circuit Simulation

Part of the book series: Computational Microelectronics ((COMPUTATIONAL))

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Abstract

Over the past decade, the downward scaling of device dimensions has resulted in a reduction in gate-oxide thickness by a factor of four. While scaling continued, the supply voltage remained constant (normally 5 V) due to the constraints of retaining compatibility with existing systems. This has resulted in increased vertical electric fields in the oxide which have already reached above 1 MV/cm in thin oxides. The scaling of channel length, meanwhile, has lead to large lateral electric field in the channel. In spite of reducing the supply voltage to 3.3 V, a strong push still remains towards higher channel electric field as scaling continues. The increased channel electric field has caused hot-carrier effects that are becoming a limiting factor in realizing submicron level VLSI. This is because hot-carrier effects impose more severe constraints on VLSI device design as device dimensions are reduced.

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  1. Digital Equipment Corporation, Hudson, MA, 01749, USA

    Dr. Narain Arora

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Arora, N. (1993). Modeling Hot-Carrier Effects. In: MOSFET Models for VLSI Circuit Simulation. Computational Microelectronics. Springer, Vienna. https://doi.org/10.1007/978-3-7091-9247-4_8

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  • DOI: https://doi.org/10.1007/978-3-7091-9247-4_8

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