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Wafer Bonding for High-Performance Logic Applications

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Wafer Bonding

Part of the book series: Springer Series in MATERIALS SCIENCE ((SSMATERIALS,volume 75))

Abstract

Shrinking the metal-oxide-semiconductor field-effect transistor (MOSFET) beyond the 50 nm technology node requires innovations to circumvent barriers due to the fundamental physics that constrains the conventional MOSFET. These innovations generally fall into two categories: new materials and new devices. Figure 5.1 depicts one view of the possible path of technological progress starting from present day 100 nm feature size technology [1,2]. In many instances, these new materials and new devices require new fabrication processes to enable their use.

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  1. K. W. Guarini
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  1. Max-Planck Institute of Microstructure Physics, Weinberg 2, 06120, Halle (Saale), Germany

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Guarini, K.W., Wong, HS.P. (2004). Wafer Bonding for High-Performance Logic Applications. In: Alexe, M., Gösele, U. (eds) Wafer Bonding. Springer Series in MATERIALS SCIENCE, vol 75. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-10827-7_5

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