Abstract
High-density hybrid integration of III–V compound optoelectronics (0E) with Complementary Metal Oxide Semiconductor (CMOS) Integrated Circuits (ICs) is emerging as a technology able to provide the features and performance required by the next generation of high functionality information processing subsystems [1–3]. Though the performance potential of III–V OE is widely recognized, high-density co-integration with CMOS and low-cost manufacturability remain the key issues, which will ultimately determine the potential of this technology for market penetration. A variety of approaches is currently proposed to achieve the goal of high-density III–V 0E-CMOS integration. Since there is not a single prevalent technology for the embodiment of such high-density OE subsystems, a comprehensive presentation of the state-of-the-art hybrid integration technologies of III–V OEs with CMOS is necessary to assess the potential of each approach.
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Kyriakis-Bitzaros, E.D., Halkias, G. (2004). High-Density Hybrid Integration of III–V Compound Optoelectronics with Silicon Integrated Circuits. In: Alexe, M., Gösele, U. (eds) Wafer Bonding. Springer Series in MATERIALS SCIENCE, vol 75. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-10827-7_10
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DOI: https://doi.org/10.1007/978-3-662-10827-7_10
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