Abstract
We present a method for formal proof of correctness of VLSI designs. Our approach is an adaptation of software verification techniques that works on circuit networks rather than program flowgraphs. The method may be viewed as a dual of Floyd’s method for program verification in which the roles of state and control are interchanged. We illustrate the approach with the semi-automatic verification of a simple NMOS design, and discuss its application to large scale VSLI designs. A proof of soundness of the method is presented in a forthcoming paper [ShS 83].
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© 1983 Computer Science Press, Inc.
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Shostak, R.E. (1983). Verification of VLSI Designs. In: Bryant, R. (eds) Third Caltech Conference on Very Large Scale Integration. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-95432-0_11
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DOI: https://doi.org/10.1007/978-3-642-95432-0_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-12369-9
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