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Aktuelle RISC-Prozessoren

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RISC-Workstation-Architekturen

Zusammenfassung

In den vorangegangenen Kapiteln wurden die Konzeption und wichtige Einzelkomponenten von RISC-Prozessoren behandelt. Dieses Kapitel stellt eine Reihe von RISC-Prozessoren vor, die heute für Workstations eingesetzt werden. Dabei wird zum einen ein Augenmerk gelegt auf Besonderheiten der Prozessorarchitektur, zum andern auf Aspekte der Integration in eine Workstation.

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Literatur

  1. Advanced Micro Devices: Am29000 32-Bit Streamlined Instruction Processor User’s Manual. Sunnyvale (CA) 1988

    Google Scholar 

  2. Advanced Micro Devices: Am29000 32-Bit Streamlined Instruction Processor Memory Design Handbook. Sunnyvale (CA) 1988

    Google Scholar 

  3. Apollo Computer Inc.: Series 10000VS Graphics Superworkstation. February 1989

    Google Scholar 

  4. Bode, A. (Hrsg.): RISC-Architekturen. Mannheim: BI-Wissenschaftsverlag, 1990 (2. Auflage)

    MATH  Google Scholar 

  5. Case, B.; Chu, P.; Johnson, M.; Baror, G.; Olson, T.; Gupta, S.: 32-Bit-Prozessor unterstützt optimierende Compiler. Elektronik 36 (1987) 6, S. 77–82

    Google Scholar 

  6. Case, B.: Intel’s i860 Sets New Performance Standard. Unusual optimization for floating-point and 3-D graphics. Microprocessor Report, March 1989; und Evaluating the i860’s Graphics Unit. Microprocessor Report, April 1989

    Google Scholar 

  7. Cohen, D.: On Holy Wars and a Plea for Peace. IEEE Computer, 14 (1981) 10, pp. 48–54

    Article  Google Scholar 

  8. Cypress: CY7C600 RISC Family Users Guide. San Jose (CA) 1988

    Google Scholar 

  9. Dewar, R. B. K.; Smosna, M.: Microprocessors, A Programmer’s View. New York 1990

    Google Scholar 

  10. Fairchild: 32-Bit-Mikroprozessor mit On-Chip Fließkomma-Verarbeitung. Design&Elektronik (1986) 17, S. 8–14

    Google Scholar 

  11. Fotland, D. A.; Shelton, J. F.; Bryg, W. R.; La Fetra, R. V.; Boschma, S. I.; Yeh, A. S.; Jacobs, E. M.: Hardware Design of the First HP Precision Architecture Computers. Hewlett-Packard Journal, March 1987, pp. 4–17

    Google Scholar 

  12. Furber, S. B,; Thomas, A. R. P.: ARM3 — a study in design for compatibility. Microprocessors and Microsystems 14 (1990) 6, pp. 407–415

    Article  Google Scholar 

  13. Garner, R. B.; Pöll, G.: SPARC — die offene RISC-Architektur. In: [HUTT 89], S. 257–270

    Google Scholar 

  14. Groves, R. D.; Oehler, R.: RISC System/6000 processor architecture. Microprocessors and Microsystems 14 (1990) 6, pp. 357–366

    Article  Google Scholar 

  15. Gunn, L.: The RISC-Processor Wars Intensify. Electronic Design 37 (1989) 6, pp. 33–41

    Google Scholar 

  16. Heath, S.: Performance improvement techniques for the M88000 RISC architecture. Microprocessors and Microsystems 14 (1990) 6, pp. 377–384

    Article  Google Scholar 

  17. Hunter, C. B.: Introducing the Clipper Architecture. IEEE Micro 7 (1987) 8, pp. 6–25

    Article  Google Scholar 

  18. Huttenloher, R.; Fey, J. (Hrsg.): ”CISC oder RISC oder ...”, Vorträge und Begleittexte zum 1. Entwicklerforum. München 1989

    Google Scholar 

  19. Intergraph Advanced Processor Division: Clipper C300, 32-Bit Compute Engine. Palo Alto 1989

    Google Scholar 

  20. Intergraph Advanced Processor Division: Clipper C300, 32-Bit Microprocessor Family. Palo Alto 1989

    Google Scholar 

  21. International Business Machines: The IBM RISC System/6000 processor. IBM Journal of Research and Development 34 (1990) 1

    Google Scholar 

  22. intel: i 860 Processor Performance, Release 1.0, March 1989

    Google Scholar 

  23. intel: i 860 64-Bit Microprocessor Programmers Reference Manual. Santa Clara (CA) 1989

    Google Scholar 

  24. James, D. V.: Multiplexed Buses: The Endian Wars Continue. IEEE Micro 10 (1990) 6, pp. 9–21

    Article  Google Scholar 

  25. Johnson, M.: System Considerations in the Design of the Am29000. IEEE Micro 7 (1987) 8, pp. 28–41

    Article  Google Scholar 

  26. Kane, G.: mips RISC Architecture. Englewood Cliffs (NJ): Prentice Hall, 1987

    Google Scholar 

  27. Khan, A.: CMOS and ECL implementations of MIPS RISC architecture. Microprocessors and Microsystems 14 (1990) 6

    Article  Google Scholar 

  28. Kohn, L.; Margulis, N.: Introducing the Intel i860 64-Bit Microprocessor. IEEE Micro 9 (1989) 8, pp. 15–30

    Article  Google Scholar 

  29. Mayer, U.; Reuveni, D.: RISC-MIPS von MIPS. In: [HUTT 89], S. 187–191

    Google Scholar 

  30. McLeod, J.: Tough Choices Ahead. Electronics, 62 (1989) 5, pp. 70–78

    Google Scholar 

  31. Melear, Ch.: The Design of the 88000 RISC Family. IEEE Micro 9 (1989) 4, pp. 26–38

    Article  Google Scholar 

  32. Motorola, Inc.: MC88100 RISC Microprocessor User’s Manual. 1988

    Google Scholar 

  33. Motorola, Inc.: MC88200 Cache / Memory Management Unit User’s Manual. 1988

    Google Scholar 

  34. Nülle, U.: Am29000, eine RISC-Familie für Embedded Controller. In: [BODE 90], S. 184–214

    Google Scholar 

  35. Piepho, R. S.; Wu, W. S.: A Comparison of RISC Architectures. IEEE Micro 9 (1989) 2, pp. 51–62

    Article  Google Scholar 

  36. Pountain, D.: The Acorn RISC Machine. Byte 11 (1986) 1, pp. 387–393

    Google Scholar 

  37. Radin, G.: The 801 Minicomputer. IBM Journal of Research and Development 27 (1983) 1, pp. 237–246

    Article  Google Scholar 

  38. Rogers, D. F.: Procedural Elements for Computer Graphics. New York 1985

    Google Scholar 

  39. Rosenbladt, P.: Hewlett-Packard Precision Architecture. In: [BODE 90], S. 307–324

    Google Scholar 

  40. Schmidberger, R.: Die M88000-Familie, eine leistungsstarke Alternative zur CISC-Technologie. In: [BODE 90], S. 325–349

    Google Scholar 

  41. Siemens AG, Bereich Halbleiter: SAB-R3000 High Performance 32-bit RISC Microcomputer. Data Sheet 02.90. München 1990

    Google Scholar 

  42. Siemens AG, Bereich Halbleiter: SAB-R3010 High Performance Floating point Coprocessor. Data Sheet 02.90. München 1990

    Google Scholar 

  43. System Performance Evaluation Cooperative (SPEC): spec Newsletter, Benchmark Results, Vol. 1, Issue 1, Fall 1989

    Google Scholar 

  44. Stelbrink, J.: Der Am29000 RISC Prozessor in Controller Applikationen. In: [HUTT 89], S. 13–17

    Google Scholar 

  45. Sun Microsystems, Inc.: The SPARC Architecture Manual. Mountain View (CA) 1987

    Google Scholar 

  46. Sun Microsystems, Inc.: Catalyst, A catalog of third-party software and hardware Mountain View (CA) 1989

    Google Scholar 

  47. Thurner, E.: Die MIPS Prozessor-Familie. In: [BODE 90], S. 379–401

    Google Scholar 

  48. VLSI Technology, Inc.: VL86C010 32-Bit RISC MPU an Peripherals User Manual Englewood Cliffs (NJ): Prentice Hall 1989

    Google Scholar 

  49. Weicker, R.: Leistungsmessungen für RISCs. In: [BODE 90], S. 145–183

    Google Scholar 

  50. Wilson, L: Reduced Instructions. Systems International, October 1988, pp. 23–33

    Google Scholar 

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Müller-Schloer, C., Schmitter, E. (1991). Aktuelle RISC-Prozessoren. In: Müller-Schloer, C., Schmitter, E. (eds) RISC-Workstation-Architekturen. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58238-7_6

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  • DOI: https://doi.org/10.1007/978-3-642-58238-7_6

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-54050-2

  • Online ISBN: 978-3-642-58238-7

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