Abstract
An infinite synchronous concurrent algorithm (isca) is an algorithm composed of infinitely many modules and channels, computing and communicating in parallel, and synchronised by a global clock. A theory of such algorithms will explore infinite parallelism and also help in understanding computation involving unbounded finite parallelism. The theory presented is a generalisation of a theory of finite synchronous concurrent algorithms, based on computable functions on many sorted algebras. We use algebras to model specifications and iscas, and epimorphisms and isomorphisms to model related notions of implementation.
We will model a hardware stack with unbounded capacity using an infinite synchronous concurrent algorithm and prove that the architecture is correct; special emphasis is placed on using algebras to formalise the various stages of the development.
First we specify equationally a class of hardware stacks that operate in time with streams of data and commands. We then present a specific algebraic model Str op (S(X)) of the hardware stack axioms that computes over an arbitrary data set X and which serves as a mathematical specification for the hardware stack. Next we define an isca and we prove that this isca implements the model Str op (S(X)) of the stack. Finally we consider the refinement of the general algebraic model and isca over the set X to an algebraic model and isca based on the set 0,1 of bits.
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McConnell, B., Tucker, J.V. (1993). Infinite Synchronous Concurrent Algorithms The Algebraic Specification and Verification of a Hardware Stack. In: Bauer, F.L., Brauer, W., Schwichtenberg, H. (eds) Logic and Algebra of Specification. NATO ASI Series, vol 94. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58041-3_9
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DOI: https://doi.org/10.1007/978-3-642-58041-3_9
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