Skip to main content

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 231))

  • 1434 Accesses

Abstract

An introduction to state assignment is presented in the chapter. Elements of two-level minimization must be included in the state assignment in order to adjust the number of implicants to the number of product terms contained in the cell. Primary and secondary merging conditions are introduced. The implicants distribution table is defined to distribute the implicants among single functions.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Czerwinski, R.: The FSMs state assignment for PAL-based matrix programmable structures. PhD thesis, Silesian University of Technology, Gliwice (2006) (in Polish)

    Google Scholar 

  2. Czerwinski, R., Kania, D.: Synthesis of finite state machines for CPLDs. International Journal of Applied Mathematics and Computer Science 19(4), 647–659 (2009)

    Article  Google Scholar 

  3. Czerwinski, R., Kania, D.: A synthesis of high speed finite state machines. Bulletin of the Polish Academy of Sciences - Technical Sciences 58(4), 635–643 (2010)

    Article  Google Scholar 

  4. Czerwinski, R., Kania, D.: Area and speed oriented synthesis of FSMs for PAL-based CPLDs. Microprocessors and Microsystems 36(1), 45–61 (2012)

    Article  Google Scholar 

  5. Debnath, D., Sasao, T.: Output phase optimization for AND-OR-EXOR PLAs with decoders and its application to design of adders. IEICE Transactions on Information and Systems E88-D(7), 1492–1500 (2005)

    Google Scholar 

  6. Deniziak, S., Sapiecha, K.: CUPLAND - a behavioral level description compiler for designing of PLD/EPLD-based systems. In: IEEE International Symposium on Circuits and Systems, ISCAS 1994, vol. 1, pp. 201–204 (1994)

    Google Scholar 

  7. Devadas, S., Newton, A.R., Ashar, P.: Exact algorithms for output encoding, state assignment and four-level boolean minimization. IEEE Transactions on Computer-Aided Design 10, 13–27 (1991)

    Article  Google Scholar 

  8. Hartmanis, J., Stearns, R.: Some dangers in the state reduction of sequential machines. Information and Control 5, 252–260 (1962)

    Article  MathSciNet  MATH  Google Scholar 

  9. Jozwiak, L.: An efficient heuristic method for state assignment of large sequential machines. Journal of Circuits, Systems, and Computers 2, 1–26 (1992)

    Article  Google Scholar 

  10. Jozwiak, L., Kolsteren, J.: An efficient method for the sequential decomposition of sequential machines. Microprocessing and Microprogramming 32, 657–664 (1991)

    Article  Google Scholar 

  11. Kam, T., Villa, T., Brayton, R., Sangiovanni-Vincentelli, A.: Synthesis of Finite State Machines: Functional Optimization. Kluver Academic Publishers, Boston (1998)

    Google Scholar 

  12. Kania, D.: Decomposition-based synthesis and its application in PAL-oriented technology mapping. In: Proceedings of 26th Euromicro Conference, pp. 138–145. IEEE Computer Society Press, Maastricht (2000)

    Google Scholar 

  13. Lala, P.: An algorithm for the state assignment of synchronous sequential circuits. Electronics Letters 14(6), 199–201 (1978)

    Article  Google Scholar 

  14. MCNC, LGSynth’91 benchmarks. Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University (1991), http://www.cbl.ncsu.edu:16080/benchmarks/LGSynth91/

  15. Perkowski, M., Malvi, R., Grygiel, S., Burns, M., Mishchenko, A.: Graph coloring algorithms for fast evaluation of curtis decomposition. In: The 36th ACM/IEEE Design Automation Conference, DAC 1999, New Orleans, pp. 225–230 (1999)

    Google Scholar 

  16. Sasao, T.: Input variable assignment and output phase optimization of PLA’s. IEEE Trans. on Computers C-33(10), 879–894 (1984)

    Article  MathSciNet  MATH  Google Scholar 

  17. Villa, T.: Encoding problems in logic synthesis. PhD thesis, University of California, Berkeley (1995)

    Google Scholar 

  18. Villa, T., Sangiovanni-Vincentelli, A.: NOVA: State assignment for finite state machines for optimal two-level logic implementation. IEEE Transactions on Computer-Aided Design 9, 905–924 (1990)

    Article  Google Scholar 

  19. Villa, T., Saldanha, T., Brayton, A., Sangiovanni-Vincentelli, A.: Symbolic two-level minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16(7), 692–708 (1997)

    Article  Google Scholar 

  20. Wan, W., Perkowski, M.: A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its applications to FPGA mapping. In: Proceedings of the Confenference on European Design Automation, pp. 230–235 (1992)

    Google Scholar 

  21. Yang, S.: Logic Synthesis and Optimization Benchmarks User Guide. Microelectronic Center of North Carolina, version 3.0 edn. (1991)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Robert Czerwinski .

Rights and permissions

Reprints and permissions

Copyright information

© 2013 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Czerwinski, R., Kania, D. (2013). Synthesis of FSMs. In: Finite State Machine Logic Synthesis for Complex Programmable Logic Devices. Lecture Notes in Electrical Engineering, vol 231. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36166-1_3

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-36166-1_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-36165-4

  • Online ISBN: 978-3-642-36166-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics