The CCSDS Decoder/Encoder Boards

Abstract

Traditionally the implementation of Telemetry Encoders and Telecommand Decoders for space has been made in hardware, at least for the last two decades. This was also the approach that was envisaged when these OBC boards had been conceptualized. But with the availability of more processing power (e.g. the LEON3FT 32-bit fault-tolerant SPARCTM V8 processor), more of the encoding and decoding tasks can be moved to software, allowing flexibility for adapting the system to on-going standardization efforts. The approach followed here in this CDPI architecture is that part of the CCSDS decoding/encoding is performed in an IP.core on FPGA hardware on the CCSDS decoder/encoder board and part of the task is done in software using libraries. This firmware and software was provided by Aeroflex Gaisler AB together with the RTEMS realtime operating system for the Aeroflex Processor-Boards cited in Chap. 2.