An On-Chip Interconnect Mechanism for Multi-processor SoC

Abstract

In this paper, a novel mechanism of on chip interconnect based on Multi-Layer AHB Lite standard is proposed. On one hand it provides the feature that multiple masters are able to access the bus simultaneously as long as there is no competition for the same slave. On the other hand this mechanism is easy to scale, reuse and consumes less resources. Distributed address decoding and master arbitration are employed. Each slave has its own data selection module with a built-in arbiter attached. All the masters are connected to the master interfaces of the data selection module and the module decides which master gains the access of the slave when a bus competition occurs. External modules can be attached to each data selection module, which makes it possible to employ different master arbitration strategies for each slave. This interconnect mechanism has ultra low latency and low arbitration costs, hence is suitable for embedded systems with strong real time requirement.