Abstract
As Extensible Markup Language (XML) becomes prevalent in cloud computing environments, it also introduces significant performance overheads. In this paper, we analyze the performance of XML parsing, identify that a significant fraction of the performance overhead is indeed incurred by memory data loading. To address this problem, we propose implementing memory-side acceleration on top of computation-side acceleration of XML parsing. To this end, we study the impact of memory-side acceleration on performance, and evaluate its implementation feasibility including bus bandwidth utilization, hardware cost, and energy consumption. Our results show that this technique is able to improve performance by up to 20% as well as produce up to 12.77% of energy saving when implemented in 32 nm technology.
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Chiu, K., Govindaraju, M., Bramley, R.: Investigating the limits of soap performance for scientific computing. In: Proceedings of the 11th IEEE International Symposium on High Performance Distributed Computing HPDC-11 (2002)
Head, M.R., Govindaraju, M., van Engelen, R., Zhang, W.: Grid scheduling and protocols—benchmarking xml processors for applications in grid web services. In: SC 2006: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing, p. 121. ACM Press, New York (2006)
Apparao, P., Iyer, R., Morin, R., Naren, N., Mahesh, B., Halliwell, D., Striberg, W.: Architectural characterization of an XML-centric commercial server workload. In: 33rd International Conference on Parallel Processing (2004)
Apparao, P., Bhat, M.: A detailed look at the characteristics of xml parsing. In: BEACON 2004: 1st Workshop on Building Block Engine Architectures for Computers and Networks (2004)
Nicola, M., John, J.: XML parsing: A threat to database performance. In: Proceeding of the 12th International Conference on Information and Knowledge Management (2003)
Intel Single-Chip Cloud Computer, http://techresearch.intel.com/ProjectDetails.aspx?Id=1
SAX Parsing Model, http://sax.sourceforge.net
W3C, Document object model (DOM) level 2 core specification, http://www.w3.org/TR/DOM-Level-2-Core
Chiu, K., Devadithya, T., Lu, W., Slominski, A.: A binary xml for scientific applications. In: Proceedings of e-Science 2005. IEEE, Los Alamitos (2005)
XimpleWare, VTD-XML: The Future of XML Processing, http://vtdxml.sourceforge.net (accessed March 10, 2007)
Lu, W., Chiu, K., Pan, Y.: A Parallel Approach to XML Parsing. In: Proceedings of The 7th IEEE/ACM International Conference on Grid Computing, Barcelona, Spain (September 2006)
Head, M.R., Govindaraju, M.: Approaching a Parallelized XML Parser Optimized for Multi-Core Processor. In: SOCP 2007, June 26, ACM, Monterey (2007)
Cameron, R.D., Herdy, K.S., Lin, D.: High Performance XML Parsing Using Parallel Bit Stream Technology. In: Proceedings of the Conference of the Center for Advanced Studies on Collaborative Research, Ontario, Canada (October 2008)
Zhao, L., Bhuyan, L.: Performance Evaluation and Acceleration for XML Data Parsing. In: Proceedings of the 9th Workshop on Computer Architecture Evaluation using Commercial Workloads, Texas, USA (2006)
Moscola, J., Lockwood, J.W.: Reconfigurable Content-based Router using Hardware-Accelerated Language Parser. The ACM Transactions on Design Automation of Electronic Systems 13 (2008)
Nag, B.: Acceleration techniques for XML processors. In: XML Conference & Exhibition (November 2004)
Dai, Z., Ni, N., Zhu, J.: A 1 Cycle-Per-Byte XML Parsing Accelerator. In: FPGA 2010 (2010)
Apache Xerces, http://xerces.apache.org/index.html
Jaleel, A., Cohn, R.S., Luk, C.K., Jacob, B.: CMP$im: A Pin-Based On-The-Fly Multi-Core Cache Simulator. In: MoBS (2008)
Shivakumar, P., Jouppi, N.P.: CACTI3.0: an integrated cache timing, power, and area model, WRL Research Report (2001)
Intel Vtune, http://software.intel.com/en-us/intel-vtune/
XML Parsing Accelerator with Intel® Streaming SIMD Extensions 4 (Intel® SSE4) (December 15, 2008), http://software.intel.com/en-us/articles/xml-parsing-accelerator-with-intel-streaming-simd-extensions-4-intel-sse4/
Lee, S., Ro, W.W.: Accelerated Network Coding with Dynamic Stream Decomposition on Graphics Processing Unit. The Computer Journal
Longshaw, A.: Scaling XML parsing on Intel architecture. Intel Software Network Resource Center (November 2008), http://www.developers.net/intelisnshowcase/view/537
Power vs. Performance: The 90 nm Inflection Point, http://www.xilinx.com/publications/archives/solution_guides/power_management.pdf
Windows Performance Analysis Tool, http://msdn.microsoft.com/en-us/performance/cc825801
Park, K., Park, J.S., Ro, W.W.: On Improving Parallelized Network Coding with Dynamic Partitioning. IEEE Transactions on Parallel and Distributed Systems 21(11), 1547–1560 (2010)
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Tang, J., Liu, S., Gu, Z., Liu, C., Gaudiot, JL. (2011). Memory-Side Acceleration for XML Parsing. In: Altman, E., Shi, W. (eds) Network and Parallel Computing. NPC 2011. Lecture Notes in Computer Science, vol 6985. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-24403-2_22
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DOI: https://doi.org/10.1007/978-3-642-24403-2_22
Publisher Name: Springer, Berlin, Heidelberg
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