Abstract
This paper presents the design methodology of high speed flash ADC by individually optimizing its various components so that the overall performance of the resulting flash ADC is improved over traditional flash ADCs. The design parameters chosen are speed, sampling frequency, power consumption, supply voltage and chip area. With high speed as a parameter, components are designed so that they operate with sampling frequency as high as 70-75 MHz. The power consumption is reduced and the ADC operates at power supply voltage down to 2.5V compatible with low power digital portion of the design. The designed ADC occupies less chip area too. All the components are designed using the 0.35μm CMOS technology.
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© 2011 Springer-Verlag Berlin Heidelberg
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Chaudhary, K., Kaushik, B.K., Pal, K. (2011). Design of High Speed Optimized Flash ADC. In: Das, V.V., Stephen, J., Chaba, Y. (eds) Computer Networks and Information Technologies. CNC 2011. Communications in Computer and Information Science, vol 142. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19542-6_42
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DOI: https://doi.org/10.1007/978-3-642-19542-6_42
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19541-9
Online ISBN: 978-3-642-19542-6
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