Abstract
Designing modern circuits comprised of millions of gates is a very challenging task. Therefore new directions are investigated for efficient modeling and verification of such systems. In this paper,we first present the concept of modeling multiple valued ALU. We demonstrate that the approach allows for efficient simulation of complex multiple valued logic systems. Secondly, we show how VHDL can be used to ensure functional correctness. A generalization of binary toggle coverage for the multiple valued logic domains is presented and evaluated. As a test case, a scalable multiple valued logic arithmetic unit is modeled and experimental results for multiple valued logic toggle coverage are given.
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References
Große, D., Fey, G., Drechsler, R.: Modeling Multi-Valued Circuits in SystemC. In: International Symposium on Multi Valued Logic, pp. 281–286 (2003)
The SystemVerilog Homepage, http://www.systemverilog.org
Muzio, J., Wesselkamper, T.: Multiple-Valued Switching Theory. Adam Hilger, Bristol (1986)
Accellera: SystemVerilog 3.1 Accellera’s extensions to Verilog, Npa, CA, pp. 1–2 (2003)
Rozon, C.: On the Use of VHDL as a Multi-Valued Logic Simulator, Royal Military College, Kingston, Ontario, Canada. IEEE, Los Alamitos (1996)
Cohen, B., Venkataramanan, S., Kumari, A.: SystemVerilog Assertions Handbook. VhdlCohen Publishing, Los Angeles (2005)
Drako, D., Cohen, P.: HDL Verification Coverage. EETimes, Global news for creators of technology (1998)
Chokler, H., Kupferman, O., Vardi, M.Y.: Coverage Metrics for Formal Verification. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol. 2860, pp. 111–125. Springer, Heidelberg (2003)
Accelera SystemVerilog 3.1a reference manual, Extension to Verilog, http://www.accellera.org/home
Drechsler, R.: Using World-Level Information in Formal Hardware Verification. Automation and Remote Control 65(6), 963–977 (2004)
Iguchi, Y., Sasao, T., Matsuura, M.: On Designs of Radix Converters Using Arithmetic Decompositions - Binary to Decimal Converters. In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, p. 32 (2007)
Ito, T., Kameyama, M.: Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation. In: 37th International Symposium on Multiple-Valued Logic, ISMVL 2007, pp. 39–44 (2007)
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Venkat Reddy, D., Paradesi Rao, C.D.V., Rajan, E.G. (2011). Toggle Coverage for ALU Using VHDL. In: Unnikrishnan, S., Surve, S., Bhoir, D. (eds) Advances in Computing, Communication and Control. ICAC3 2011. Communications in Computer and Information Science, vol 125. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-18440-6_59
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DOI: https://doi.org/10.1007/978-3-642-18440-6_59
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-18439-0
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