Abstract
We present an analog-VLSI neural network for image recognition which features a dimensionality reduction network and a classification stage. We implement local learning rules to train the network on chip or program the coefficients from a computer, while compensating for the negative effects of device mismatch and circuit nonlinearity. Our experimental results show that the circuits perform closely to equivalent software implementations, reaching 87% accuracy for face classification and 89% for handwritten digit classification. The circuit dissipates 20mW and occupies 2.5mm2 of die area in a 0.35μm CMOS process.
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Carvajal, G., Valenzuela, W., Figueroa, M. (2009). Image Recognition in Analog VLSI with On-Chip Learning. In: Alippi, C., Polycarpou, M., Panayiotou, C., Ellinas, G. (eds) Artificial Neural Networks – ICANN 2009. ICANN 2009. Lecture Notes in Computer Science, vol 5768. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04274-4_45
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DOI: https://doi.org/10.1007/978-3-642-04274-4_45
Publisher Name: Springer, Berlin, Heidelberg
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