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Board Level Reliability

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Memories in Wireless Systems

Part of the book series: Signals and Communication Technology ((SCT))

Abstract

In recent years, manufacturing smaller and lighter devices has been the trend for both mobile phones and all other portable products. One of the most important factors leading to weight reduction has been the adoption of both BGAs (ball grid arrays) and CSPs (chip scale packages).

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References

  1. Darveaux R, Syed A Reliability of area array solder joints inbending. White Paper disponibile consultando il sito internet http://www.amkor.com

  2. Electronic Industries Association of Japan (1992) Standard of Electronic Industries Association of Japan: Mechanical stress test methods for semiconductor surface mounting devices

    Google Scholar 

  3. Shetty S, Lehtinen V, Dasgupta A, Halkola V, Reinikainen T (1999) Effect of bending on chip scale package interconnects. ASME International Mechanical Engineering Congress, Nashville

    Google Scholar 

  4. Leicht L, Skipor A (1998) Mechanical cycling fatigue of PBGA package interconnects. Proceedings of the International Symposium on Microelectronics

    Google Scholar 

  5. Juso H, Yamaji Y, Kimura T, Fujita K, Kada M (2000) Board levelreliability of CSP. Proc IEEE ECTC

    Google Scholar 

  6. Perera UD (1999) Evaluation of reliability of μBGA solder joints through twisting and bending. Microelectron Reliab No. 39

    Google Scholar 

  7. Rooney DT, Castello NT, Cibulsky M, Abbott D, Xie D (2004) Materials characterization of the effect of mechanical bending on area array package interconnects. Microelectron Reliab No. 4

    Google Scholar 

  8. Tee TY, Ng HS, Luan J, Yap D, Loh K, Pek E, Lim CT, Zhong Z (2004) Integrated modeling and testing of fine-pitch CSP under board level drop test, bend test and thermal cycling test. ICEP Conference, Japan

    Google Scholar 

  9. JEDEC (2003) Board level drop test method of components for handheld electronic products. Standard JESD22-B111

    Google Scholar 

  10. JEDEC (2001) Mechanical shock. Standard JESD22-B104-B

    Google Scholar 

  11. Chiu A, Pek E, Lim CT, Luan J, Tee TY Zhong Z (2004) Modal analysis and spectrum analysis of PCB under drop impact. SEMICON Singapore

    Google Scholar 

  12. Pek E, Lim CT, Tee TY, Luan J, Zhong Z (2004) Novel numerical and experimental analysis of dynamic responses under board level drop test. EuroSIME Conference, Belgium

    Google Scholar 

  13. Pek E, Lim CT, Tee TY, Luan J, Zhong Z (2004) Advanced experimental and simulation techniques for analysis of dynamic responses during drop impact. 54th ECTC Conference, USA

    Google Scholar 

  14. Abe M, Kumai T, Higashiguchi Y, Tsubone K, Mishiro K, Ishikawa S (2002) Effect of the drop impact on BGA/CSP package reliability. Microelectron Reliab No. 42

    Google Scholar 

  15. Ng HS, Tee TY, Zhong Z (2003) Design for enhanced solder joint reliability of integrated passives device under board level drop test and thermal cycling test. 5th EPTC Conference, Singapore

    Google Scholar 

  16. Luan J, Yap D, Loh K, Pek E, Lim CT, Tee TY, Ng HS, Zhong Z (2004) Integrated modeling and testing of fine-pitch CSP under board level drop test, bend test, and thermal cycling test. ICEP Conference, Japan

    Google Scholar 

  17. Lim CT, Pek E, Tee TY, Ng HS, Zhong Z (2003) Board level drop test and simulation of TFBGA packages for telecommunication applications. 53rd ECTC Conference, USA

    Google Scholar 

  18. Huang CY, Liao CC, Zheng PJ, Hung SC, Wu JD, Ho SH (2002) Board level reliability of a stacked CSP subjected to cyclic bending. Microelectron Reliab No. 42

    Google Scholar 

  19. Tee TY, Ng HS (2000) Board level solder joint reliability modeling on TfBGA package. International Conference on Electronic Reliability

    Google Scholar 

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© 2008 Springer-Verlag Berlin Heidelberg

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Radente, S., Borsini, S. (2008). Board Level Reliability. In: Micheloni, R., Campardo, G., Olivo, P. (eds) Memories in Wireless Systems. Signals and Communication Technology. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-79078-5_8

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  • DOI: https://doi.org/10.1007/978-3-540-79078-5_8

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-79077-8

  • Online ISBN: 978-3-540-79078-5

  • eBook Packages: EngineeringEngineering (R0)

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