Abstract
Modern processors use speculative execution to improve performance. However, speculative execution requires a checkpoint/restore mechanism to repair the machine’s state whenever speculation fails. Existing checkpoint/restore mechanisms do not scale well for processors with relatively large windows (i.e., 128 or more). This work presents Turbo-ROB, a checkpoint/restore recovery accelerator that can complement or replace existing checkpoint/restore mechanisms. We show that the Turbo-ROB improves performance and reduces resource requirements compared to a conventional Re-order Buffer mechanism. For example, on the average, a 64-entry TROB matches the performance of a 512-entry ROB, while a 128- and a 512-entry TROB outperform the 512-entry ROB by 6.8% and 9.1% respectively. We also demonstrate that the TROB improves performance with register alias table checkpoints effectively reducing the need from more checkpoints and the latency and energy increase these would imply.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Akkary, H., Rajwar, R., Srinivasan, S.: An Analysis of Resource Efficient Checkpoint Architecture. ACM Transactions on Architecture and Code Optimization (TACO) 1(4) (December 2004)
Akkary, H., Rajwar, R., Srinivasan, S.: Checkpoint Processing and Recovery: Towards Scalable Instruction Window Processors. In: Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (November 2003)
Aragon, J.L., Gonzalez, J., Gonzalez, A., Smith, J.E.: Dual Path Instruction Processing. In: Proceedings of the 16th International Conference on Supercomputing, pp. 220–229 (June 2002)
Burger, D., Austin, T.: The Simplescalar Tool Set v2.0, Technical Report UW-CS-97-1342., Computer Sciences Department, University of Wisconsin-Madison (June 1997)
Cristal, A., Ortega, D., Llosa, J., Valero, M.: Kilo-Instruction Processors. In: Proceedings The 5th International Symposium on High Performance Computing (ISHPC-V) (October 2003)
Grunwald, D., Klauser, A., Manne, S., Pleszkun, A.: Confidence Estimation for Speculation Control. In: Proceedings of the 25th Annual International Symposium on Computer Architecture (June 1998)
Hwu, W.W., Patt, Y.N.: Checkpoint Repair for Out-of-Order Execution Machines. In: Proceedings of the 14th Annual Symposium on Computer Architecture (June 1987)
Jacobsen, E., Rotenberg, E., Smith, J.E.: Assigning Confidence to Conditional Branch Predictions. In: Proceedings of the 29th Annual International Symposium on Microarchitecture (Decmber 1996)
Jimenez, D.A., Lin, C.: Composite Confidence Estimators for Enhanced Speculation Control, Technical Report TR-02-14, Department of Computer Sciences, The University of Texas at Austin (January 2002)
Manne, S., Klauser, A., Grunwald, D.: Pipeline Gating: Speculation Control for Energy Reduction. In: Proceedings of the 25th Annual International Symposium on Computer Architecture (June 1998)
Moshovos, A.: Checkpointing Alternatives for High Performance, Power-Aware Processors. In: Proceedings of the IEEE International Symposium Low Power Electronic Devices and Design (ISLPED) (August 2003)
Safi, E., Akl, P., Moshovos, A., Veneris, A., Arapoyianni, A.: On the Latency, Energy and Area of Superscalar Renaming Tables. In: Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Devices (August 2007)
Smith, J., Pleszkun, A.: Implementing Precise Interrupts in Pipelined Processors. IEEE Transactions on Computers 37(5) (May 1988)
Sohi, G.S.: Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers. IEEE Transactions on Computers (March 1990)
Yeager, K.C.: The MIPS R10000 Superscalar Microprocessor. IEEE MICRO (1996)
Zhou, P., Onder, S., Carr, S.: Fast Branch Misprediction Recovery in Out-of-Order Superscalar Processors. In: Proceedings of the International Conference on Supercomputing (June 2005)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Akl, P., Moshovos, A. (2008). Turbo-ROB: A Low Cost Checkpoint/Restore Accelerator. In: Stenström, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2008. Lecture Notes in Computer Science, vol 4917. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77560-7_18
Download citation
DOI: https://doi.org/10.1007/978-3-540-77560-7_18
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77559-1
Online ISBN: 978-3-540-77560-7
eBook Packages: Computer ScienceComputer Science (R0)