Abstract
In order to solve the system performance bottleneck of a 3D graphics acceleration SoC, we exploit design space exploration on performance evalu-ation and benchmark characteristics using SystemC. We find out the bottleneck according to the simulation results of 9 hardware/software configurations and find out the tradeoffs between different configurations. The performance issues of SoC have been explored under the low-cost constraints, such as cache size effect, hardware accelerations and memory traffic. In conclusions, we provide the performance/cost tradeoffs and 3D graphics benchmark features for designing a 3D graphics SoC.
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Yeh, TC., Ho, TY., Chen, HY., Huang, IJ. (2007). SystemC-Based Design Space Exploration of a 3D Graphics Acceleration SoC for Consumer Electronics. In: Kuo, TW., Sha, E., Guo, M., Yang, L.T., Shao, Z. (eds) Embedded and Ubiquitous Computing. EUC 2007. Lecture Notes in Computer Science, vol 4808. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77092-3_46
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DOI: https://doi.org/10.1007/978-3-540-77092-3_46
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-77091-6
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