Abstract
In this paper, we propose a gate-level NBTI delay degradation model, where the stress voltage variability due to PMOS transistors’ stacking effect is considered for the first time. Experimental results show that our gate-level NBTI delay degradation model results in a tighten upper bound for circuit performance analysis. The traditional circuit degradation analysis leads to on average 59.3% overestimation. The pin reordering technique can mitigate on average 6.4% performance degradation in our benchmark circuits.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Borkar, S.: Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. Micro, IEEE 25(6), 10–16, 0272–1732 (2005)
Huard, V., Denais, M., Parthasarathy, C.: NBTI degradation: From physical mechanisms to modelling. Microelectron. Reliab. 46(1), 1–23 (2006)
Kufluoglu, H., Alam, M.A.: Theory of interface-trap-induced NBTI degradation for reduced cross section MOSFETs. IEEE Trans. Electron Devices 53(5), 1120–1130 (2006)
Wittmann, R., Puchner, H., Hinh, L., Ceric, H., Gehring, A., Selberherr, S.: Impact of NBTI-driven parameter degradation on lifetime of a 90nm p-MOSFET. In: Proc. Intl. Integrated Reliab. Workshop Final Report, pp. 99–102 (2005)
Reddy, V., Krishnan, A.T., Marshall, A., Rodriguez, J., Natarajan, S., Rost, T., Krishnan, S.: Impact of negative bias temperature instability on digital circuit reliability. Microelectron. Reliab. 45(1), 31–38 (2005)
Kumar, S., Kim, C., Sapatnekar, S.: Impact of NBTI on SRAM Read Stability and Design for Reliability. In: Proc. ISQED, pp. 210–218 (2006)
Ogawa, S., Shiono, N.: Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. Physical Review B 51(7), 4218–4230 (1995)
Alam, M., Mahapatra, S.: A comprehensive model of PMOS NBTI degradation. Microelectron. Reliab. 45(1), 71–81 (2005)
Mahapatra, S., Saha, D., Varghese, D., Kumar, P.: On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress. IEEE Trans. Electron Device 53(7), 1583–1592 (2006)
Chen, G., Li, M., Ang, C., Zheng, J., Kwong, D.: Dynamic NBTI of p-MOS transistors and its impact on MOSFET scaling. IEEE Electron Dev. Lett. 23(12), 734–736 (2002)
Mahapatra, S., Bharath Kumar, P., Dalei, T., Sana, D., Alam, M.: Mechanism of negative bias temperature instability in CMOS devices: degradation, recovery and impact of nitrogen. In: IEDM Tech. Dig., pp. 105–108 (2004)
Paul, B., Kang, K., Kufluoglu, H., Alam, M., Roy, K.: Impact of NBTI on the temporal performance degradation of digital circuits. IEEE Electron Dev. Lett. 26(8), 560–562 (2005)
Kumar, S., Kim, C., Sapatnekar, S.: An Analytical Model for Negative Bias Temperature Instability. In: Proc. IEEE/ACM ICCAD, pp. 493–496 (2006)
Vattikonda, R., Wang, W., Cao, Y.: Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design. In: Proc. DAC, pp. 1047–1052 (2006)
Bhardwaj, S., Wang, W., Vattikonda, R., Cao, Y., Vrudhula, S.: Predictive Modeling of the NBTI Effect for Reliable Design. In: Proc. CICC, pp. 189–192 (2006)
Luo, H., Wang, Y., He, K., Luo, R., Yang, H., Xie, Y.: Modeling of PMOS NBTI Effect Considering Temperature Variation. In: Proc. ISQED, pp. 139–144 (2007)
Nanoscale Integration and Modeling Group, ASU: Predictive Technology Model (PTM)
Paul, B., Kang, K., Kufluoglu, H., Alam, M., Roy, K.: Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits. In: Proc. DATE, vol. 1, pp. 1–6 (2006)
Stathis, J., Zafar, S.: The negative bias temperature instability in MOS devices: A review. Microelectron. Reliab. 46(2-4), 270–286 (2006)
Sultania, A., Sylvester, D., Sapatnekar, S.: Transistor and pin reordering for gate oxide leakage reduction in dual Tox circuits. In: Proc. ICCD, pp. 228–233 (2004)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2007 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Luo, H., Wang, Y., He, K., Luo, R., Yang, H., Xie, Y. (2007). A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. In: Azémard, N., Svensson, L. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2007. Lecture Notes in Computer Science, vol 4644. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-74442-9_16
Download citation
DOI: https://doi.org/10.1007/978-3-540-74442-9_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-74441-2
Online ISBN: 978-3-540-74442-9
eBook Packages: Computer ScienceComputer Science (R0)