Abstract
In this paper, we characterized the TPC-H benchmark on an Itanium II processor. Our experiment results clearly demonstrate: (1) On Itanium II processor, the memory stall time is dominanted by first level (L1) instruction cache and third level (L3) data cache misses; (2) Index can reduces L3 data cache misses dramatically but increases a slightly more Condition Branch Instruction misprediction (BMP) rate. These revealed characteristics are expected to benefit database performance optimizations and database architecture design on next-generation processors.
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Liu, D., Wang, S., Qin, B., Gong, W. (2007). Characterizing DSS Workloads from the Processor Perspective. In: Chang, K.CC., et al. Advances in Web and Network Technologies, and Information Management. APWeb WAIM 2007 2007. Lecture Notes in Computer Science, vol 4537. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-72909-9_26
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DOI: https://doi.org/10.1007/978-3-540-72909-9_26
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-72908-2
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