Abstract
The suitability of the multi-master VME bus for the design of a memory channel architecture for high performance computing is discussed. A moderately scalable cluster-based parallel computing system and its communication network based on this architecture are described next. The development of a thirty two processor parallel computing system and its programming environment are outlined. The details of the intra-cluster and inter-cluster communication channels in this system and the interface for using them are presented. Some parallel applications in computational fluid dynamics and the speed-ups achieved are presented next. A discussion on the experiences of building this system and further efforts underway to enhance its scalability conclude the paper.
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References
Fox, G.C., Johnson, M.A., Lyzenga, G.A., Otto, S.W., Salman, J.K., Walker, D.W.: Solving Problems on Concurrent Processors. Prentice Hall, New York (1988)
Hwang, K., Briggs, F.A.: Computer Architecture and Parallel Processing. McGraw Hill, New York (1994)
Xu, Z., Hwang, K.: Early prediction of MPP performance: The SP2, T3D and Paragon experiences. Parallel Computing 22, 917–942 (1996)
Anderson, T.E., Culler, D.E., Patterson, D.A.: The NOW team.: A case for NOW (Networks of Workstations). IEEE Micro, 54–64 (February 1995)
Tandiary, F., Kothari, S.C., Dixit, A., Walter Anderson, E.: Batrun: Utilising Idle Workstations for Large-Scale Computing. IEEE Parallel and Distributed Technology: Systems and Applications 2(4), 41–48 (1996)
Miguel, J., Arruabarrena, A., Beivide, R., Gregorio, J.A.: Assessing the Performance of the New IBM SP2 Communication Subsystem. IEEE Parallel and Distributed Technology: Systems and Applications 4(4), 12–22 (1996)
Gillett, R.B.: Memory Channel Network for PCI. IEEE Micro 16(1), 12–18 (1996)
Kahaner, D.K.: Parallel computing in India. IEEE Parallel and Distributed Technology: Systems and Applications 4(3), 7–11 (1996)
SPARC RISC User’s Guide, Ross Technology Inc., USA (1993)
VMIVME-5550 Reflective Memory Board, Document No. 500-035550-000C, VME Microsystems International Corporation, USA (1994)
Sharma, M., et al.: PACE+ User Manual, Report No. ANURAG/PACE+/01, ANURAG, Hyderabad, India (1997)
Xu, Z., Hwang, K.: Modelling Communication Overhead: MPI and MPL Performance on the IBM SP2. IEEE Parallel and Distributed Technology: Systems and Applications 4(1), 9–23 (1996)
Sharma, M., Mandal, A.: Communication Overhead Model for Point-to-Point Communications on PACE+, Report No.ANURAG/PACE+/02,ANURAG, Hyderabad, India (1998)
Sinha, P.K.: The Solution of Flow Problems Around Complex Configuration Using Euler Code VEEMA on Parallel Computer PACE+. In: Proceedings of the Third Asian Computational Fluid Dynamics Conference, Bangalore, India (December 1998)
Singh, K.P., Uthup, B., Ravishanker, L.: Parallelisation of Euler and N-S Code on 32 Node Parallel Supercomputer PACE+. In: ADA/DRDO-DERA Workshop on CFD, Bangalore, India (September 1997)
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© 1999 Springer-Verlag Berlin Heidelberg
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Sharma, M., Mandal, A., Rao, B.S., Athithan, G. (1999). VME Bus-Based Memory Channel Architecture for High Performance Computing. In: Banerjee, P., Prasanna, V.K., Sinha, B.P. (eds) High Performance Computing – HiPC’99. HiPC 1999. Lecture Notes in Computer Science, vol 1745. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-46642-0_7
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DOI: https://doi.org/10.1007/978-3-540-46642-0_7
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