Abstract
High speed and low cost configuration loading methods for a coarse grain multicontext reconfigurable device DRP(Dynamically Reconfigurable Processor) are proposed and implemented. In these methods, the configuration data is compressed on the host computer before loading, and decoded at the time of loading by circuits implemented on a part of logics. Unlike conventional reconfigurable device, the logic for decoder circuits is switched with application circuits immediately after loading in multicontext reconfigurable devices. Thus, the circuit does not use a real estate of the chip during the execution. Two compression methods LZSS-ARC and Selective coding are implemented and evaluated. LZSS-ARC achieves better compression ratio, while Selective coding can work at the same frequency of the data loading.
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References
Fujii, T., et al.: A Dynamically Reconfigurable Logic Engine with a Multi-Context/Multi-Mode Unified-Cell Architecture. In: Proc. International Solid State Circuit Conference (1999)
Motomura, M.: A Dynamically Reconfigurable Processor Architecture. Microprocessor Forum (October 2002)
Master, P.: The Age of Adaptive Computing Is Here. In: Proc. of FCCM, pp.1–3 (2002)
Ling, X.-P., Amano, H.: WASMII: A Data Driven Computer on a Virtual Hardware. In: Proc. FCCM, pp. 33–42 (1993)
Horta, E.L., Lockwood, J.W., Partour, D.: Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration. In: Proc. of DAC (June 2002)
Ziv, J., Lempel, A.: A universal algorithm for sequential data compression. IEEE Transactions on Information Theory, IT 23(3), 337–343 (1977)
Storer, J.A., Syzmanski, T.G.: Data compression via textual substitution. J. of ACM 29(4), 928–951 (1982)
William, D., Wilson, S., Hauck, S.: Runlength Compression Techniques for FPGA Configurations. In: Proc. FCCM, pp.276–277 (1999)
Li, Z., Hauck, S.: Configuration Compression for Virtex FPGA. In: Proc. FCCM, pp.143–154 (2001)
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Kitaoka, T., Amano, H., Anjo, K. (2003). Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_18
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DOI: https://doi.org/10.1007/978-3-540-45234-8_18
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