Abstract
Although methods for dynamic run-time FPGA reconfiguration have been proposed, few address the problems associated with increasing data-path delays due to a full or partial reconfigurations. In this paper, a method is proposed that enables specific timing requirements to be maintained within a reconfigurable architecture, by using logic-module partitioning and known-delay interconnection modules. This system allows data-paths of varying widths to be routed effectively between device modules along paths that are fixed in both length and position. Further, the technique may be regarded as extending the Xilinx Modular Design tools methodology to support run-time scenarios.
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Carline, D., Coulton, P. (2003). A Controlled Data-Path Allocation Model for Dynamic Run-Time Reconfiguration of FPGA Devices. In: Y. K. Cheung, P., Constantinides, G.A. (eds) Field Programmable Logic and Application. FPL 2003. Lecture Notes in Computer Science, vol 2778. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-45234-8_133
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DOI: https://doi.org/10.1007/978-3-540-45234-8_133
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