Abstract
Modern general-purpose processors employ multi-port register files and multiple functional units to support instruction-level parallelism. Fixed (1 word per cycle) bandwidth between cache and register-file might limit processor’s ability in spatial/temporal utilization. This paper presents an experimental study of conventional super-scalar processor architecture to determine benefits that we can expect to achieve by enabling variable data bandwidth between the L1 data cache and the register file. Our results demonstrate that by changing the bus width to 64, 128 and 256 bits we can reduce data traffic between the 32KB register-file and 32KB cache up to 29%, 45% and 53%, respectively, while lowering the program execution time by 8%, 13% and 17% on average in comparison to conventional single-word cache access. An adaptive bandwidth cache capable of adjusting the cache bandwidth to workload variation is also proposed.
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Hamayasu, K., Moshnyaga, V.G. (2004). Impact of Register-Cache Bandwidth Variation on Processor Performance. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_18
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DOI: https://doi.org/10.1007/978-3-540-30102-8_18
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