Abstract
This paper implements a new digit-serial systolic array for the computation of a power-sum operation and a new digit-serial systolic divider using the proposed systolic power-sum array in GF(2m) with the standard basis representation. Both of the architectures possess features of regularity, modularity, and unidirectional data flow. As a consequence, they have low AT complexity and are well suited to VLSI implementation with fault-tolerant design. Furthermore, the proposed power-sum array is also possible to select the digit-size of the regular square form.
This research was supported by University IT Research Center Project.
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© 2004 Springer-Verlag Berlin Heidelberg
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Lee, WH., Lee, KJ., Yoo, KY. (2004). New Digit-Serial Systolic Arrays for Power-Sum and Division Operation in GF(2m). In: Laganá, A., Gavrilova, M.L., Kumar, V., Mun, Y., Tan, C.J.K., Gervasi, O. (eds) Computational Science and Its Applications – ICCSA 2004. ICCSA 2004. Lecture Notes in Computer Science, vol 3045. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24767-8_67
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DOI: https://doi.org/10.1007/978-3-540-24767-8_67
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22057-2
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