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On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors

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High Performance Computing (ISC High Performance 2018)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10876))

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Abstract

This paper presents refinements to the execution-cache-memory performance model and a previously published power model for multicore processors. The combination of both enables a very accurate prediction of performance and energy consumption of contemporary multicore processors as a function of relevant parameters such as number of active cores as well as core and Uncore frequencies. Model validation is performed on Intel Sandy Bridge-EP, Broadwell-EP, and AMD Epyc processors. Production-related variations in chip quality are demonstrated through a statistical analysis of the fit parameters obtained on one hundred Broadwell-EP CPUs of the same model. Insights from the models are used to explain the performance- and energy-related behavior of the processors for scalable as well as saturating (i.e., memory-bound) codes. In the process we demonstrate the models’ capability to identify optimal operating points with respect to highest performance, lowest energy-to-solution, and lowest energy-delay product and identify a set of best practices for energy-efficient execution.

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Notes

  1. 1.

    Consider, e.g., the 18-core Broadwell-EP chip, which offers 17 different Uncore and 12 different CPU core frequencies, for which a total of 3672 measurements (each with a non-negligible runtime to reach operating temperature equilibrium) are required. In contrast, setting up the model requires only four, six, and nine measurements on the AMD Epyc, Intel Sandy Bridge-EP, and Broadwell-EP processors, respectively.

  2. 2.

    The term Uncore refers to all parts of the chip that are not part of the core design, such as, e.g., shared last-level cache, ring interconnect, and memory controllers.

  3. 3.

    http://tiny.cc/LIKWID.

  4. 4.

    The coefficient of variation is used to measure the relative variance of a sample. It is defined as the ratio of the standard deviation \(\sigma \) to the mean \(\mu \) of a sample.

  5. 5.

    For n active cores, the probability of a core’s memory access encountering a busy bus is \(u(n-1)\); when the bus is busy, the penalty \(p_\mathrm {0}\), which increases with the number of cores, is applied.

  6. 6.

    On Sandy and Ivy Bridge processors the Uncore is clocked at the same frequency as the CPU cores and can thus only be set indirectly.

  7. 7.

    Wall clock time can also be used, which essentially mirrors the plot about the y axis.

  8. 8.

    https://www.anleitungen.rrze.fau.de/hpc/meggie-cluster/.

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Hofmann, J., Hager, G., Fey, D. (2018). On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors. In: Yokota, R., Weiland, M., Keyes, D., Trinitis, C. (eds) High Performance Computing. ISC High Performance 2018. Lecture Notes in Computer Science(), vol 10876. Springer, Cham. https://doi.org/10.1007/978-3-319-92040-5_2

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  • DOI: https://doi.org/10.1007/978-3-319-92040-5_2

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