Abstract
Ensuring trustworthiness of modern computing systems is a critical and inherently complex problem. Trust assurance techniques today span the entire design life cycle, require highly diverse expertise and skill set for each technique, and are overall grossly inadequate. This chapter provides a glimpse of some of the trust assurance techniques used in current industrial practice and discusses their complexities and limitations.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
S. Bhunia, S. Ray, S. Sur-Kolay (eds.), Fundamentals of IP and SoC Security: Design, Validation, and Debug (Springer, Cham, 2017)
E.M. Clarke, O. Grumberg, D.A. Peled, Model-Checking (The MIT Press, Cambridge, 2000)
EMVCo: EMV®; Specifications. See http://www.emvco.com
A. Gupta, Formal hardware verification methods: a survey. Formal Methods Syst. Des. 2(3), 151–238 (1992)
JasperGold Security Verification Path App. See https://www.cadence.com/content/cadence-www/global/en_US/home/tools/system-design-and-verification/formal-and-static-verification/jasper-gold-verification-platform/security-path-verification-app.html
S. Krstic, J. Yang, D.W. Palmer, R.B. Osborne, E. Talmor, Security of SoC firmware load protocol, in IEEE HOST (2014)
E. Messmer, RSA security attack demo deep-fries Apple Mac components (2014). See http://www.networkworld.com/news/2014/022614-rsa-apple-attack-279212.html
Microsoft Threat Modeling & Analysis Tool version 3.0 (2009)
A. Nahiyan, K. Xiao, D. Forte, Y. Jin, M. Tehranipoor, AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs, in Design Automation Conference (2016)
NIST: Federal information processing standards publication: security requirements for cryptographic modules. See http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.140-2.pdf
S. Ray, J. Bhadra, Security challenges in mobile and IoT systems, in IEEE System-on-Chip Conference (2016)
S. Ray, Y. Jin, A. Raychowdhury, The changing computing paradigm with Internet-of-Things: a tutorial introduction. IEEE Des. Test Comput. 33(2), 76–96 (2016)
S. Ray, S. Bhunia, P. Mishra, Security validation in modern SoC designs, in Fundamentals of IP and SoC security: design, validation, and debug, ed. by S. Bhunia, S. Ray, S. Sur-Kolay (Springer, Cham, 2017), pp. 9–28
S. Ray, E. Peeters, M. Tehranipoor, S. Bhunia, System-on-Chip platform security assurance: architecture and validation. Proc. IEEE (2017). https://doi.org/10.1109/JPROC.2017.2714641
Reverse engineering integrated circuits with degate. See http://www.degate.org
S. Skorobogatov, C. Woods, Breakthrough silicon scanning discovers backdoor in military chip, in CHES (2012), pp. 23–40
J. Srivatanakul, J.A. Clark, F. Polac, Effective security requirements analysis: HAZOPs and use cases, in 7th International Conference on Information Security (2004), pp. 416–427
A. Takanen, J.D. DeMott, C. Mille, Fuzzing for Software Security Testing and Quality Assurance (Artech House, Norwood, 2008)
M. Tehranipoor, U. Guin, D. Forte, Counterfeit Integrated Circuits: Detection and Avoidance (Springer, Cham, 2014)
The Common Criteria. See http://www.commoncriteriaportal.org/cc/
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG
About this chapter
Cite this chapter
Ray, S. (2018). Hardware Trust in Industrial SoC Designs: Practice and Challenges. In: Bhunia, S., Tehranipoor, M. (eds) The Hardware Trojan War. Springer, Cham. https://doi.org/10.1007/978-3-319-68511-3_15
Download citation
DOI: https://doi.org/10.1007/978-3-319-68511-3_15
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-68510-6
Online ISBN: 978-3-319-68511-3
eBook Packages: EngineeringEngineering (R0)