Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length

Abstract

This paper proposes a deterministic method to construct 5-regular geometric graphs with short average distance under the constraint such that the set of vertices is a subset of $\mathbb {N}\times \mathbb {N}$ and the length of each edge is at most 4. This problem is motivated by the design of efficient floor plan of parallel computers consisting of a number of computing nodes arranged on a two-dimensional array. In such systems, the degree of vertices is determined by the number of ports of the routers and the edge length is limited by a certain value determined by the cycle time. The goodness of the resulting geometric graph is evaluated by the average shortest path length (ASPL) between vertices which reflects the average communication delay between computing nodes. The idea of the proposed method is to arrange the basic component derived from (3, g)-cage in a two-dimensional manner and to connect adjacent components by parallel edges of length 4 each. The result of numerical calculations shows that the average distance in the resulting graph is close to the lower bound so that the gap to the lower bound is less than 0.98 when the number of vertices is 432000.

This work was partially supported by MIC/SCOPE (152103004), JSPS KAKENHI (15K00144, 16H02807) and JST CREST.

A Application of the Result Graph to Off- and On-chip Interconnection Networks

Recent interconnection networks potentially have tight constraints on link length especially when conventional electric media is used. Short-cable design is still preferred in various interconnection networks, such as supercomputers [1, 20]. This constraint efficiently reduces power consumption of links, thus giving a significant impact on the design of interconnection networks. For example, when 40 Gbps passive electric cables whose length can be up to 7 m are used, the Mellanox IS5024 36-port InfiniBand switch saves the power consumption to 111.54 W, while active optical cables impose the same switch for 200.4 W [13, 14]. Since a supercomputer has a large number of cables (remind that the K computer has 200,000 cables reaching 1,000 km), the network design under cable geometric constraints becomes important for low-power interconnection network design.

The link length limitation is also a severe issue in on-chip interconnection network designs, especially with an advanced CMOS process technology. In general, a wire delay increases with the square of the wire length. Inserting repeater buffers on the wire can mitigate the wire delay, while it increases the energy consumption on the wire. Thus the longest wire length between on-chip routers should be carefully tuned under given design constraints, such as operating frequency, dimensions of cores, wire delay, and wire energy. However, it is most likely to be automatically determined by underlying regular topologies (e.g., 2-D mesh and torus). As an alternative to such regular topologies, a low-latency topology optimized for a given longest wire length parameter would become an attractive design option when the design constraints severely affect the cost and the performance.

The above fact motivates us to explore the use of short links in the off- and on-chip network topology design. This is just the application of the result graph in this study to such interconnection networks.