Abstract
Over the past few years, numerous real-time and embedded systems have been adopting multi-core architectures for either better performances, or energy efficiency. For the case of real-time applications, where tasks can have critical deadlines, it is desirable to ensure the schedulability of the application statically, taking into account the possible software and hardware failures. While a lot of effort have been made to handle software misbehaviours, resilience to hardware failures has often been overlooked.
In this paper, we propose to study the schedulability of multi-core applications. Specifically, we want to check statically whether or not a real-time system will be able to meet the deadlines of its most critical tasks, even when one or more of its cores are offline. In order to achieve this goal, we translate the schedulability problem into a state space exploration, using Data Decision Diagrams to support the computation and analysis of such state space.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Baruah, S., Guo, Z.: Mixed-criticality scheduling upon varying-speed processors. In: 2013 IEEE 34th Real-Time Systems Symposium (RTSS), pp. 68–77. IEEE (2013)
Bryant, R.E.: Graph-based algorithms for boolean function manipulation. IEEE Trans. Comput. C–35(8), 677–691 (1986)
Burns, A., Davis, R.: Mixed criticality systems-a review. Department of Computer Science, University of York, Technical report (2013)
Cire, A.A., van Hoeve, W.J.: Multivalued decision diagrams for sequencing problems. Oper. Res. 61(6), 1411–1428 (2013)
Cirinei, M., Bini, E., Lipari, G., Ferrari, A.: A flexible scheme for scheduling faulttolerant real-time tasks on multiprocessors. In: 2007 IEEE International Parallel and Distributed Processing Symposium, pp. 1–8 (2007)
Clarke, E.M., Emerson, E.A., Sistla, A.P.: Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Trans. Program. Lang. Syst. 8(2), 244–263 (1986)
Couvreur, J.-M., Encrenaz, E., Paviot-Adet, E., Poitrenaud, D., Wacrenier, P.-A.: Data decision diagrams for Petri Net analysis. In: Esparza, J., Lakos, C.A. (eds.) ICATPN 2002. LNCS, vol. 2360, pp. 101–120. Springer, Heidelberg (2002)
Hong, S., Kordon, F., Paviot-Adet, E., Evangelista, S.: Computing a hierarchical static order for decision diagram-based representation from P/T Nets. In: Jensen, K., Donatelli, S., Kleijn, J. (eds.) ToPNoC V. LNCS, vol. 6900, pp. 121–140. Springer, Heidelberg (2012)
Hostettler, S., Marechal, A., Linard, A., Risoldi, M., Buchs, D.: High-level petri net model checking with alpina. Fundam. Inform. 113(3–4), 229–264 (2011). http://dx.doi.org/10.3233/FI-2011-608
Jeff, B.: Big. little system architecture from arm: saving power through hetero-geneous multiprocessing and task context migration. In: Proceedings of the 49th Annual Design Automation Conference, pp. 1143–1146. ACM (2012)
Jensen, A.R., Lauritzen, L.B., Laursen, O.: Optimal task graph scheduling with binary decision diagrams (2004)
Kordon, F., Garavel, H., Hillah, L.M., Hulin-Hubard, F., Linard, A., Beccuti, M., Hamez, A., Lopez-Bobeda, E., Jezequel, L., Meijer, J., Paviot-Adet, E., Rodriguez, C., Rohr, C., Srba, J., Thierry-Mieg, Y., Wolf, K.: Complete Results for the 2015 Edition of theModel Checking Contest (2015). http://mcc.lip6.fr/2015/results.php
Linard, A., Paviot-Adet, E., Kordon, F., Buchs, D., Charron, S.: polydd: Towards a framework generalizing decision diagrams. In: 10th International Conference on Application of Concurrency to System Design, ACSD 2010, Braga, Portugal, 21–25 June 2010. pp. 124–133 (2010). http://dx.doi.org/10.1109/ACSD.2010.17
Lopez-Bobeda, E., Colange, M., Buchs, D.: Building a symbolic model checker from formal language description. In: 2015 15th International Conference on Application of Concurrency to System Design (ACSD), pp. 50–59 (2015)
Mushtaq, H., Al-Ars, Z., Bertels, K.: Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems. In: 2011 IEEE 6th International Design and Test Workshop (IDT), pp. 12–17 (2011)
Nikolic, B., Bletsas, K., Petters, S.M.: Hard real-time multiprocessor scheduling resilient to core failures. In: 2015 IEEE 21st International Conference on Embedded and Real-Time Computing Systems and Applications, pp. 122–131 (2015)
Pathan, R.M.: Fault-tolerant real-time scheduling using chip multiprocessors. Proc. Suppl. vol. EDCC (2008)
Rice, M., Kulhari, S.: A survey of static variable ordering heuristics for efficient bdd/mdd construction. University of California, Technical report (2008)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Racordon, D., Buchs, D. (2016). Verifying Multi-core Schedulability with Data Decision Diagrams. In: Crnkovic, I., Troubitsyna, E. (eds) Software Engineering for Resilient Systems. SERENE 2016. Lecture Notes in Computer Science(), vol 9823. Springer, Cham. https://doi.org/10.1007/978-3-319-45892-2_4
Download citation
DOI: https://doi.org/10.1007/978-3-319-45892-2_4
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-45891-5
Online ISBN: 978-3-319-45892-2
eBook Packages: Computer ScienceComputer Science (R0)